Patents Examined by Christopher A Daley
  • Patent number: 11729020
    Abstract: A transmitting/receiving device for a bus system and a method for reducing an oscillation tendency in the case of coupled-in interferences, in particular, in the transition between different bus states. The transmitting/receiving device has a transmitting stage for transmitting a transmit signal to a first bus wire of a bus of the bus system, and for transmitting the transmit signal to a second bus wire of the bus, and an oscillation reduction module for damping an oscillation of a bus signal arising at terminals for the bus wires when the transmitting/receiving device acts as the transmitter of the transmit signal. The oscillation reduction module includes a first resistor, which is switchable between the first bus wire and a terminal for ground, and the oscillation reduction module including a second resistor, which is switchable between the second bus wire and a terminal for a voltage supply of the bus system.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 15, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Axel Pannwitz, Steffen Walker
  • Patent number: 11720519
    Abstract: A user station for a serial bus system and a method for transmitting a message in a serial bus system. The user station includes a communication control device for transmitting messages to a bus of the bus system and/or for receiving messages from the bus of the bus system, and a bit rate switchover unit for switching over a bit rate of the messages from a first bit rate in a first communication phase to a second bit rate for a second communication phase. The bit rate switching unit is designed to switch the bit rate from the first bit rate over to the second bit rate, due to an edge of a predetermined bit sequence that includes one bit of the first communication phase and one bit of the second communication phase.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 8, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arthur Mutter, Florian Hartwich
  • Patent number: 11720506
    Abstract: The embodiments of the present disclosure relate to a device and method for inspecting process and an electronic control device. The device for inspecting process may include a converting controller configuring to be controlled for, when a preset operation is performed in a serial communication, converting into at least one process monitoring message by inputting a specific value into a dummy area included in at least one message corresponding to the preset operation, and an inspecting controller configuring to be controlled for inspecting a process based on the process monitoring message.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: August 8, 2023
    Assignee: HL Klemove Corp.
    Inventors: Jong Gyu Park, Han-Sik Kim, Seung Gap Choi
  • Patent number: 11716224
    Abstract: A module for managing communication among instrumentation and control devices associated with a system, and a method for using the module, enable interconnection of various devices across multiple network buses, and filtering of messages travelling between devices on disparate buses. Buses may be established wirelessly in addition to via wired connections. Additional devices may connect to a pluggable terminal interface integrated with the module. The terminal interface may connect to a configurable variety of interconnecting circuits appropriate for various types of terminal devices. An associated user interface may enable a user to configure various parameters pertaining to connected devices, including alerts to be issued when certain parameters exceed thresholds, and actions to be taken upon issuance of such alerts.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: August 1, 2023
    Assignee: Airmar Technology Corporation
    Inventors: Marshal W. Linder, Alan J. Testani
  • Patent number: 11714768
    Abstract: The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 1, 2023
    Assignee: ebm-papst Mulfingen GmbH & Co. KG
    Inventors: Andreas Fessel, Markus Humm
  • Patent number: 11704263
    Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: July 18, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sriramakrishnan Govindarajan, Kishon Vijay Abraham Israel Vijayponraj, Mihir Narendra Mody
  • Patent number: 11704272
    Abstract: A method for operating a transfer device for a differential bus system, including a first bus connection and a second bus connection for connecting to a transfer medium of the differential bus system. The method includes: ascertaining a first variable that characterizes a voltage associated with a first bus line of the bus system, ascertaining a second variable that characterizes a voltage associated with a second bus line of the bus system, ascertaining a third variable that characterizes a sum of the first variable and the second variable for a first bus state, ascertaining a fourth variable that characterizes a sum of the first variable and the second variable for a second bus state, the second bus state being different from the first bus state.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: July 18, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Felix Lang, Steffen Walker
  • Patent number: 11706049
    Abstract: A subscriber station for a serial bus system including a communication control device for controlling a communication with another subscriber station and a transceiver device for sending a transmit signal produced by the communication control device as a frame to a bus of the bus system. The bit time of a signal sent to the bus in the first communication phase differs from a bit time of a signal sent in the second communication phase. The communication control device produces the transmit signal, in a first operating mode, for a first frame that is designed according to a specified communication protocol with which other subscriber stations in the bus system communicate, and is designed to produce the transmit signal, in a second operating mode, for a second frame that assigns to at least one bit a different function than is assigned to the bit in the specified communication protocol.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: July 18, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arthur Mutter, Florian Hartwich
  • Patent number: 11698876
    Abstract: A processing device in a memory sub-system receives a plurality of requests to perform a plurality of input/output (IO) operations corresponding to a plurality of logical devices associated with a memory device and assigns the plurality of requests to respective queues associated with the plurality of logic devices. The processing device further iteratively processes the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Horia C. Simionescu, Xiaodong Wang, Venkata Yaswanth Raparti
  • Patent number: 11700143
    Abstract: A user station for a serial bus system. The user station includes a communication control device for controlling a communication of the user station with at least one other user station, and a transceiver device for transmitting a transmission signal, generated by the communication control device, onto a bus, so that for a message that is exchanged between user stations of the bus system, the bit time of a signal transmitted onto the bus in the first communication phase is different from a bit time of a signal transmitted in the second communication phase. The communication control device generates the transmission signal according to a frame in which a field for a header check sum and a field for a frame check sum are provided, and computers the header check sum from all bits in the header of a frame that is formed for the message, except fixed stuff bits.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 11, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arthur Mutter, Florian Hartwich
  • Patent number: 11698880
    Abstract: A system on chip including a first master circuit, a second master circuit, a routing circuit, a bridge control circuit, and a peripheral circuit is provided. The first master circuit provides a first command. The second master circuit provides a second command. The routing circuit receives the first command and the second command and provides an output command. The bridge control circuit receives the output command and stores an attribute setting value. In response to the routing circuit receiving the first command and the first command pointing to the peripheral circuit, the routing circuit uses the first command as the output command and the bridge control circuit determines whether attribute information of the output command matches the attribute setting value. In response to the attribute information of the output command matching the attribute setting value, the bridge control circuit provides the output command to the peripheral circuit.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 11, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Shun-Hsiung Chen
  • Patent number: 11698879
    Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Swadesh Choudhary, Robert G. Blankenship, Siva Prasad Gadey, Sailesh Kumar, Vinit Mathew Abraham, Yen-Cheng Liu
  • Patent number: 11693801
    Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: July 4, 2023
    Assignee: RAMBUS INC.
    Inventor: Scott C. Best
  • Patent number: 11681646
    Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: June 20, 2023
    Assignee: Drut Technologies Inc.
    Inventors: Jitender Miglani, Dileep Desai
  • Patent number: 11675726
    Abstract: A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes, based on the annotated first bus guide and the second bus guide, generating, by at least one processor, a plurality of guidance directories corresponding to a plurality of routes through the plurality of layout blocks for placing the plurality of repeaters at the plurality of layout blocks on the identified plurality of areas on the first bus guide or the second bus guide.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: June 13, 2023
    Assignee: Synopsys, Inc
    Inventors: Kai-Ping Wang, Songmei Chen, Ying Liu, Xiaolin Yuan
  • Patent number: 11677581
    Abstract: A subscriber station for a serial bus system and a method for communicating in a serial bus system. The subscriber station includes a communication control device for controlling a communication of the subscriber station with at least one other subscriber station of the bus system, a transmitting/receiving device for receiving a transmission signal generated by a communication control device of a subscriber station of the bus system in a frame from a bus of the bus system and for generating a reception signal from the received frame, and a connection quality block for detecting and evaluating a quality of a communication connection to a subscriber station of the bus system from the reception signal generated by the transmitting/receiving device by using at least two time quanta, into which the bit time of a bit of the generated reception signal is subdivided.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 13, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arthur Mutter, Florian Hartwich, Steffen Walker
  • Patent number: 11675724
    Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: John E. Maroney, Christopher J. Bueb
  • Patent number: 11665019
    Abstract: An apparatus for transmitting data over a bus system, having a storage device for at least temporary storage of messages transmittable over the bus system. The apparatus is designed to check at least one message, stored in the storage device, for at least one criterion and to alter at least one portion of the message based on the check.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: May 30, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Arthur Mutter, Florian Hartwich, Franz Bailer, Ramona Jung, Thomas Enderle
  • Patent number: 11658144
    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11657009
    Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun