Patents Examined by Christopher B. Shin
  • Patent number: 10191867
    Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM), and an interface circuit for interfacing the system to an external posted transaction bus. Each processor has the same address map. Each fetches instructions from SLMEM, and accesses data from/to SLMEM. A processor can initiate a read transaction on the posted transaction bus by doing an AHB-S bus write to a particular address. The AHB-S write determines the type of transaction initiated and also specifies an address in a shared memory in the interface circuit. The interface circuit uses information from the AHB-S write to generate a command of the correct format. The interface circuit outputs the command onto the posted transaction bus, and then receives read data back from the posted transaction bus, and then puts the read data into the shared memory at the address specified by the processor in the original AHB-S bus write.
    Type: Grant
    Filed: September 4, 2016
    Date of Patent: January 29, 2019
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 10185695
    Abstract: Techniques and mechanisms for providing test functionality at an integrated circuit (IC) chip. In an embodiment, the IC chip includes protocol stacks variously coupled each between a switch fabric and other switch circuitry which is configurable to selectively implement, at least in part, either of an operational mode and a test mode. The operational mode facilitates communication, via the switch circuitry, between a first protocol stack and physical layer circuitry. The test mode instead enables communication, between the first protocol stack and a second protocol stack, of test packet information which is based on a test packet received from the switch fabric. In another embodiment, the protocol stacks support communication according to a Thunderboltâ„¢ protocol.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Yonah Lasker
  • Patent number: 10187507
    Abstract: A centralized resource manager manages the routing of audio or visual information within a device, including a handheld device such as a smartphone. The resource manager evaluates data-driven policies to determine how to route audio or visual information to or from various input or output components connected to the device, including headphones, built-in speakers, microphones, bluetooth headsets, cameras, and so on. Among the data considered in the policies are connection status data, indicating if a device is connected, routing status data, indicating if a device is permitted to route information to or from a component, and grouping data, indicating logical relationships between various components. Components may be considered inherently routable, automatically routable, or optionally routable. Numerous other uses exist for such data, including providing simpler and more logical management interfaces.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 22, 2019
    Assignee: Apple Inc.
    Inventors: Andrew Rostaing, Anthony J. Guetta, Greg Chapman
  • Patent number: 10162775
    Abstract: A system and method for cross-controller data storage operations comprises interconnecting a responding storage controller and an owning storage controller with a direct memory access (DMA) capable fabric, the responding storage controller and the owning storage controller each comprising an interface from a data bus connected to the DMA capable fabric, configuring and implementing a shared DMA address space in accordance with the DMA capable fabric, the shared DMA address space including memory on the responding storage controller and the owning storage controller, the shared DMA address space being one of a symmetric or asymmetric address space, and exposing one or more local buffers of the responding storage controller and one or more local buffers of the owning storage controller through the shared DMA address space.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 25, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Mark Kampe, Can Chen, Jinshui Liu, Wei Zhang
  • Patent number: 10152431
    Abstract: A system and process of adjusting units coupled to a control element which includes, installing the unit at a selected location. A parameter can be entered from a displaced user operable device. The unit can be directed to carry out a selected function. Performance can be evaluated whether an additional parameter alteration is required based on a predetermined criterion.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: December 11, 2018
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Kevin G. Piel, Kenneth G. Eskildsen
  • Patent number: 10152281
    Abstract: A method of transparently inserting a virtual storage layer into a Fiber channel based storage area network (SAN) while maintaining continuous I/O operations is provided. A device is inserted between a host entity and a first storage device. The device identifies a plurality of first paths between the host entity and the first storage device, and defines a plurality of second paths by defining, for each first path among the plurality of first paths, a corresponding second path between the host entity and a second storage device. The device determines, for each of the plurality of first paths, a respective first state. The device establishes, for each of the second paths among the plurality of second paths, a second state based on the first state of the corresponding first path. The device redirects, to the second storage device, communications directed from the host entity to the first storage device, via the plurality of second paths.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 11, 2018
    Assignee: CIRRUS DATA SOLUTIONS, INC.
    Inventors: Wayne K. Lam, Wai T. Lam, Yikshum Tam, Lin Zhu
  • Patent number: 10146714
    Abstract: A method for synchronizing transactions between components of a system on chip includes monitoring a partial sequence of transactions that use AXI communication protocol for a stream of address calls and a streams of transfer batches. For each of the address calls and transfer batches identified by the same unique identifier, extracting an anticipated an anticipated number of transfers per batch from each of the address calls of the stream of address calls, and recursively, comparing the anticipated numbers of transfers extracted from the address calls of the stream of address calls with the number of transfers in the transfer batches of the stream of batches. Pairing a predetermined number of consecutive address calls of the stream of address calls with consecutive batches of the stream of batches based on the comparison.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 4, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Yoav Lurie
  • Patent number: 10089275
    Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel, Shaul Yohai Yifrach
  • Patent number: 8447719
    Abstract: A method of compiling causal rules into continuations for use in root cause analysis of a system comprising a plurality of inter-related elements, comprising defining observable events occurring on system elements; defining at least one of a cause and a result of each of the events; defining causal rules, each rule describing a causal relationship between an event and one of its cause and its result; and compiling the causal relationships as continuations in a continuation passing style (CPS) for use in analyzing the root cause of subsequent observed events symptomatic of at least one problem on the system.
    Type: Grant
    Filed: September 27, 2008
    Date of Patent: May 21, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Bob Bethke, Srikanth Natarajan
  • Patent number: 8447897
    Abstract: A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: May 21, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kun Xu, Tommi M. Jokinen, David B. Kramer
  • Patent number: 8438324
    Abstract: Embodiments of the present invention relate to a (e.g., hybrid) redundant array of independent disks (RAID)-based storage control board having a fiber channel interface controller. Specifically, the present invention relates to a storage control board having a RAID controller with a peripheral component interconnect express (PCI-e) interface and a fiber channel interface controller. In one embodiment, the RAID controller is coupled to an input/output (I/O) hub and a set (at least one) of PCI-e slots, which themselves can receive cards such as a fiber channel (FC) add-on card, a serial attached small component system interface (SAS) add-on card, or a PCI-e bridge add-on card. The I/O hub can be coupled to a set of processors, each of which can be coupled to a main memory module or the like.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: May 7, 2013
    Assignee: Taejin Info Tech Co., Ltd.
    Inventor: Byungcheol Cho
  • Patent number: 8433828
    Abstract: Techniques for controlling a touch input device using an accessory communicatively coupled to the device are disclosed. In one aspect, an accessibility framework is launched on the device. An accessory coupled to the device is detected. Receipt of input from the accessory is enabled. An accessibility packet is received from the accessory. The accessibility packet includes an accessibility command and one or more parameters. The accessibility packet is processed to extract the first accessibility command and the one or more parameters. Input is generated for the accessibility framework based on the accessibility command and the one or more parameters. In some implementations, the device also sends accessibility commands to the accessory, either in response to accessibility commands received from the accessory or independent of any received accessibility commands.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 30, 2013
    Assignee: Apple Inc.
    Inventors: Christopher B. Fleizach, Paul Holden, Eric Taylor Seymour, Emily Clark Schubert, Lawrence Bolton, Sylvain René Louboutin
  • Patent number: 8429315
    Abstract: In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 23, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Keyur Chudgar, Satish Sathe
  • Patent number: 8423688
    Abstract: A configuration performing processing of dividing a file into a plurality of pieces and transmitting the same even when a size of the file is large in transfer of files (input/output) between computers on a network is provided. A multi-thread file input/output system includes a first module performing processing of reading data from an input file, dividing the data into a plurality of pieces, and transmitting the plurality of pieces to a network by multi-thread processing in a transmitter computer; and a second module performing processing of receiving the plurality of pieces from the network and integrating and writing the same to an output file 5 in a receiver computer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 16, 2013
    Assignee: Hitachi Systems, Ltd.
    Inventor: Mineyuki Tamura
  • Patent number: 8407671
    Abstract: Circuits, methods, and apparatus for testing media player accessories. One example includes an accessory validation system including hardware, firmware, and software. This example provides two test modes, referred to a sniff mode and an emulation mode. In the sniff mode, a test box may be inserted between an accessory and a media player. Traffic between the accessory and media player may be monitored and the presence of errors may be determined. In the emulation mode, the accessory validation system hardware emulates a media player. The emulator provides various types of responses to the accessory that would otherwise occur infrequently with an actual media player. The tests to be completed in these modes are compiled based on the category of functions that an accessory maker wishes to claim for the accessory. These category claims are then converted into a number of rules. From these rules, specific tests are generated.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: March 26, 2013
    Assignee: Apple Inc.
    Inventors: John Ananny, Jesse Dorogusker
  • Patent number: 8402182
    Abstract: Peripherals and data processing systems are disclosed which can be configured to interact based upon sensor data. In one embodiment, a peripheral, which is configured to be used with a data processing system, includes an interface to couple the peripheral to the data processing system, and at least one sensor, such as a proximity sensor, to sense a user of the peripheral, and a processor coupled to the interface and to the at least one sensor, wherein the processor configures the peripheral in response to data from the at least one sensor. The peripheral may communicate sensor data from its sensors to the data processing system, which may be a wireless PDA, and the data processing system analyzes the sensor data from its sensors and from the peripheral's sensors to decide how to configure the peripheral and/or the data processing system based on the sensor.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 19, 2013
    Assignee: Apple Inc.
    Inventors: Nicholas Kalayjian, Stanley Rabu, Jeffrey Terlizzi
  • Patent number: 8402193
    Abstract: A storage router and method for providing virtual local storage on remote storage devices to devices are provided. A plurality of devices, such as workstations, are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and receives and processes native low level block protocol requests from the devices connected to the first transport medium to access allocated storage.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: March 19, 2013
    Assignee: Crossroads Systems, Inc.
    Inventors: Geoffrey B. Hoese, Jeffry T. Russell
  • Patent number: 8402194
    Abstract: A storage router and method for providing virtual local storage on remote storage devices to devices are provided. Devices are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and controls access from the devices connected to the first transport medium to the storage space on the remote storage devices in accordance with the map and using native low level block protocol.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 19, 2013
    Assignee: Crossroads Systems, Inc.
    Inventors: Geoffrey B. Hoese, Jeffry T. Russell
  • Patent number: 8397000
    Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 12, 2013
    Assignee: Altera Corporation
    Inventors: Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
  • Patent number: 8392892
    Abstract: An application analyzing method includes extracting a variable corresponding to a particular input data item and information regarding a value of the variable by analyzing a plurality of source programs constituting an application, record information of a database used by the application, and execution control information of the application, and outputting, based on the variable and the information regarding the value of the variable extracted in the extracting, information regarding a presumed value with respect to the input data item as presumed requirement information.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: March 5, 2013
    Assignee: Fujitsu Limited
    Inventors: Akihiko Matsuo, Yoshiharu Maeda, Kohji Wada, Shigeo Suto