Patents Examined by Christopher B. Shin
  • Memory system and method of operating the memory system
    Patent number: 11150838
    Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command set in response to a host command and output the command set to the memory device. The interface circuit is configured to: receive the command set, transmit the received command set to the semiconductor memory, when the received command set corresponds to the semiconductor memory, perform a blocking operation so that the received command set is not transmitted to the semiconductor memory, when the received command set corresponds to the interface circuit, and perform an on-die termination operation, a ZQ calibration operation, or a driving force control operation of the interface circuit in response to the received command set corresponding to the interface circuit.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
  • Bandwidth efficient access to persistent storage in a distributed storage system
    Patent number: 11144461
    Abstract: An apparatus comprises at least one processing device configured, in conjunction with processing of an input-output (IO) operation by a first storage node of a distributed storage system, where processing of the IO operation requires access to at least one persistent storage device remote from the first storage node but local to a second storage node of the distributed storage system, to send a request from the first storage node to the second storage node identifying data associated with the operation. The processing device determines a buffer of the second storage node that is allocated for use by the second storage node for temporary storage of the data, and utilizes the buffer to provide the data to the second storage node to allow the second storage node to write the data, and/or to obtain the data from the second storage node after the second storage node has read the data.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: October 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Alex Soukhman, Lior Kamran
  • Local cache size control in a storage array
    Patent number: 11138123
    Abstract: Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to: analyze input/output (I/O) operations received by a storage system; dynamically predict anticipated I/O operations of the storage system based on the analysis; and dynamically control a size of a local cache of the storage system based on the anticipated I/O operations.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 5, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: John Krasner, Ramesh Doddaiah
  • Memory system
    Patent number: 11126379
    Abstract: A memory system includes a memory device including a plurality of segments; a processor configured to generate a Read-Modify-Write (RMW) command on a target segment address corresponding to a target segment among the plurality of segments; a scheduler configured to receive the RMW command from the processor and schedule the RMW command; and a RMW unit configured to execute the RMW command on the memory device according to control of the scheduler, wherein the scheduler compares, when a plurality of RMW commands received from the processor are pending, target segment addresses of the plurality of RMW commands to re-order the plurality of RMW commands.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Method and system for organizing NAND blocks and placing data to facilitate high-throughput for random writes in a solid state drive
    Patent number: 11126561
    Abstract: One embodiment provides a system for facilitating data placement. The system receives, by a computing device, data to be written to a non-volatile memory, wherein the data is associated with a first logical block address. The system performs, based on the first logical block address, a search in a mapping table for an entry which indicates a first physical block address associated with a first physical unit. A respective physical unit can comprise a plurality of blocks of data across a plurality of channels of the non-volatile memory. The system writes the data to a second physical block address in the first physical unit. The system updates the entry by replacing the first physical block address with the second physical block address.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 21, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Shu Li
  • Compressed extent versions
    Patent number: 11119682
    Abstract: Examples include compressed extent versions. Examples may create an empty target virtual volume tree having a tree structure of a source virtual volume tree of a source storage system, the source virtual volume tree comprising source base and source snapshot virtual volumes, each representing respective versions of a plurality of extents, wherein each of the extents corresponds to a different portion of an address space of the source base virtual volume. Examples may include compressed extent collections, each comprising a compressed representation of multiple populated versions of a single extent from the source base and snapshot virtual volumes, the multiple populated versions compressed relative to one another.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: September 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ayman Abouelwafa, Salil Gokhale, Srinivasa D. Murthy
  • Fabric driven non-volatile memory express subsystem zoning
    Patent number: 11113001
    Abstract: In some examples, fabric driven NVMe subsystem zoning may include receiving, from a non-volatile memory express (NVMe) Name Server (NNS), a zoning specification that includes an indication of a host that is to communicate with a given NVMe subsystem of an NVMe storage domain. Based on the zoning specification, the host may be designated as being permitted to connect to the given NVMe subsystem of the NVMe storage domain. An NVMe connect command may be received from the host. Based on the designation and an analysis of the NVMe connect command, a connection may be established between the given NVMe subsystem of the NVMe storage domain and the host.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 7, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Asutosh Satapathy, Komateswar Dhanadevan, Krishna Babu Puttagunta, Vivek Agarwal, Rupin T. Mohan, Govind Chandru Rathod
  • Bit masking valid sectors for write-back coalescing
    Patent number: 11099987
    Abstract: A method comprising identifying a portion of data in a first memory component to be written to a managed unit of a second memory component and determining whether an additional portion of data in the first memory component associated with the managed unit is stored at the cache memory. The method further includes generating a bit mask identifying locations of the managed unit associated with the portion of data and the additional portion of data and performing, based on the bit mask, a write operation comprising the portion of data and the additional portion of data to the managed unit of the second memory component.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Trevor C. Meyerowitz, Dhawal Bavishi, Fangfang Zhu
  • Memory system supporting programmable selective access to subsets of parallel-arranged memory chips for efficient memory accesses
    Patent number: 11093416
    Abstract: A memory system supporting programmable selective access to subsets of parallel-arranged memory chips for efficient memory accesses is disclosed. A memory controller is programmable to selectively control a number of parallel-arranged memory chips in the memory system activated in a grouping for a memory access based on a memory access policy. The memory access policy is based on the number of memory chips to be activated to achieve the desired data line size for a given memory access. This programmability of the memory controller is made possible by separate dedicated chip select lines being coupled to each memory chip. Being able to only activate a subset of the memory chips for a memory access allows conservation of data bus bandwidth and power that would otherwise by consumed by asserting unused data on the data buses.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Qualcomm Intelligent Solutions, Inc
    Inventors: David Stewart Dunning, Shekhar Yeshwant Borkar, Nitin Yeshwant Borkar, Matthew Scott Radecic
  • Performance threshold
    Patent number: 11093136
    Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 17, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
  • Memory controller and memory system having the same
    Patent number: 11086528
    Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a command generator configured to generate a command in response to a request received from a host; a throttling manager configured to activate or inactivate a delay signal by comparing a current throughput of data that is being currently processed in a memory system and a request throughput of data that is to be processed in the memory system; and a completion signal output circuit configured to delay an output of a completion signal with respect to the request when the delay signal is activated, and outputs the completion signal when the delay signal is inactivated.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Seok Hoon Jung, Min Seong Chae
  • Storage device for interfacing with host and method of operating the host and the storage device
    Patent number: 11080217
    Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Min Lee, Sung-Ho Seo, Hwa-Seok Oh, Kyung-Phil Yoo, Seong-Yong Jang
  • Adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks
    Patent number: 11074185
    Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Non-volatile memory data write management
    Patent number: 11068165
    Abstract: An open block management apparatus, system, and method for non-volatile memory devices is disclosed herein, providing improved performance for namespace-based host applications. The namespace identifier is applied to determine the open blocks to which to direct data from storage commands. One benefit of the disclosed technique is fewer de-fragmentation operations and more efficient memory garbage collection. Another benefit is the ability to secure private allocations of physical memory without needing to assign a partition or implement hardware isolation.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Shay Benisty, Ariel Navon, Judah Gamliel Hahn
  • Systems and methods of distributed backup and recovery on a private network
    Patent number: 11068195
    Abstract: The systems and methods of distributed backup on a private network, comprising: establishing a secure and encrypted private network with one or more profile computing devices; establishing a whitelist of trusted profiles on a first profile computing device; selecting two or more profiles from the whitelist to backup information from the first profile computing device; tracking any updates to the network address of the selected profiles for backup; tracking information on remote profile computing devices that originated from the first profile computing device; sending differential information for backup that does not exist on other remote profile computing devices to the selected profile computing devices.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: July 20, 2021
    Assignee: Whitestar Communications, Inc.
    Inventor: Billy Gayle Moon
  • System and method for a restoration of on-premise backups to a cloud-based service
    Patent number: 11068196
    Abstract: A method for performing a backup operation includes obtaining a restoration request, and in response to the restoration request: identifying a first set of backups, wherein each backup in the first set of backups is associated with requested data, mounting the first set of backups from the backup storage system, performing data mining on the first set of backups to obtain a hierarchical structure, providing a set of options to a client based on the hierarchical structure, obtaining a selection from the client, wherein the selection is a portion of the set of options, obtaining selected content based on the selection, wherein the selected content is in a source format, converting the selected content from a source format to a target format to obtain target formatted user-specified content, and initiating a transfer of the target-formatted user-specified content to a cloud-based service.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Aneesh Kumar Gurindapalli, Deepthi Urs, Mahesh Reddy Appireddygari Venkataramana, Swaroop Shankar DH
  • Method and system for storing and managing states of a computer
    Patent number: 11068194
    Abstract: Disclosed herein are systems and method for storing and managing states of a computing device. In one aspect, an exemplary method comprises determining an initial state of the computing device, wherein the initial state includes states of all storage sectors associated with the computing device, storing the determined initial state in an initial blocks storage, for each new state that corresponds to a respective point in time subsequent to a time at which the initial state was determined, creating a snapshot, where the created snapshot includes a difference between the initial state and the new state, for each created snapshot, identifying a set of changed blocks that are in storage, and storing the changed blocks of data to a changed blocks storage, and creating a snap-map for any number of consecutive changes based on the sets of changed blocks corresponding to the respective consecutive changes.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Acronis International GmbH
    Inventors: Oleg Melnikov, Vladimir Strogov, Alexey Sergeev, Serguei Beloussov, Alexey Dod, Stanislav Protasov
  • Memory device and associated flash memory controller
    Patent number: 11068421
    Abstract: The present invention provides a memory device including a connector and a flash memory controller. The connector is configured to connect to a first host and a second host. The flash memory controller is configured to select one of the first host and the second host based on a selection signal, and the flash memory controller only processes commands from the selected one of the first host and the second host, and accesses a flash memory module based on the commands.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 20, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Hung-Pin Tsai, Chih-Chien Lin, Chien-An Chen
  • Tree-based snapshots
    Patent number: 11055179
    Abstract: Some examples relate generally to computer architecture software for information security and, in some more particular aspects, to tree-based snapshots and detecting malware therein.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 6, 2021
    Assignee: RUBRIK, INC.
    Inventor: Sahil Chauhan
  • Apparatus and method for retaining firmware in memory system
    Patent number: 11036421
    Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Jeen Park, Jung-Ae Kim, Duk-Rae Lee