Abstract: A data processing system and a method of operating the same may include a host system and a memory system. The host system may include a host memory and a host controller, and the memory system may include a memory controller and a nonvolatile memory device. The memory controller may include a data attribute determination circuit and a memory selection circuit. The data attribute determination circuit may be configured to determine an attribute of write data received from the host controller. The memory selection circuit may be configured to select, based on the determined attribute of the write data, any one of the host memory and the nonvolatile memory device as a location where the write data is to be stored.

Abstract: Debug trace statements from a firmware are captured during a boot cycle of a computer executing the firmware. The debug trace statements are written to a motherboard's Serial Peripheral Interface (“SPI”) device. A microcontroller's SPI device receives the debug trace statements from the motherboard's SPI device, transforms the data format of the debug trace statements, and transmits the transformed debug trace statements over a serial communications port of the microcontroller.

Abstract: Embodiments are described for performing an uninterrupted backup in a storage system in view of one or more abort events. A backup agent receives writes one or more data blocks to a write latch. A parent interrupt service routine (ISR) polls for abort events. In response to an abort event, an intermediate interrupt is generated that spawns a child processes for each process of the backup. The intermediate ISR logs each child ISR, the process it is responsible for, and the intermediate interrupt, for later restoration of the backup state. After a recovery of the above event, then each child ISR can be called to restore its state. After restoring the state, the backup agent resumes the backup from where the abort event was detected. The child ISRs are re-entrant. If another abort event is detected, the backup state can again be saved and later resumed from that state.

Abstract: Systems and methods for deleting backup pieces associated with an application such as a database application. Backup pieces are identified and deleted from the database records and from the backup application.

Abstract: According to one embodiment, a memory system controls a plurality of parallel access units each of which includes a plurality of blocks belonging to the different nonvolatile memory chips. The memory system stores information indicating address conversion rules prescribed such that the number of defective blocks included in the parallel access units is equal to or smaller than a first number. Each of the address conversion rules indicates a mathematical rule for converting a block address to be sent to each of the nonvolatile memory chips into another block address. An address conversion circuit in the memory system converts each of block addresses to be sent to each nonvolatile memory chip into another block address, based on each mathematical rule.

Abstract: A device, which may be a peripheral device or a host computing device, comprises a communication interface, a memory and a processor. The processor is arranged to detect imminent disconnection of a communication link between the peripheral device and the host computing device and in response to detecting the imminent disconnection of the communication link, to trigger a data transfer from the host computing device to the peripheral device via the communication interface. The data transfer defines, at least in part, a fixed output data set which, after disconnection, is output via an output device in the peripheral device.

Abstract: Examples include a computing system having an input/output (I/O) device including a plurality of counters, each counter operating as one of a completion counter and a trigger counter, a processing device; and a memory device. The memory device stores instructions that, in response to execution by the processing device, cause the processing device to represent a plurality of triggered operations of collective communication for high-performance computing executable by the I/O device as a directed acyclic graph stored in the memory device, with triggered operations represented as vertices of the directed acyclic graph and dependencies between triggered operations represented as edges of the directed acyclic graph; traverse the directed acyclic graph using a first process to identify and mark vertices that can share a completion counter; and traverse the directed acyclic graph using a second process to assign a completion counter and a trigger counter for each vertex.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. When power supply is started with respect to the controller, the controller reads file allocation data indicative of an allocation position of a file stored in the nonvolatile memory from the nonvolatile memory, generates information indicating that the controller is permitted to read a system file stored in the nonvolatile memory, and generates information indicating that the controller is not permitted to read a first user file already written in the nonvolatile memory before the power supply, and generates information indicating that the controller is permitted to read a second user file written in the nonvolatile memory after the start of the power supply.

Abstract: There is provision of a processing device including an instruction decoder and an arithmetic unit configured to process an immediate instruction for instructing a calculation of a product of an immediate value and a constant. In response to receiving the immediate instruction, the instruction decoder generates a first shift control information and a second shift control information based on the constant. The arithmetic unit generates a first shifted value by bit-shifting the immediate value received from the instruction decoder based on the first shift control information, and a second shifted value by bit-shifting the immediate value or a complement of the immediate value based on the second shift control information. By performing an addition of the first shifted value and the second shifted value, the arithmetic unit calculates the product.

Abstract: A graphics processing unit may, in accordance with a kernel, determine that at least a first packet is written to a memory buffer of the graphics processing unit by a network interface card via a direct memory access, process the at least the first packet in accordance with the kernel, and provide a first notification to a central processing unit that the at least the first packet is processed in accordance with the kernel. The graphics processing unit may further determine that at least a second packet is written to the memory buffer by the network interface card via the direct memory access, process the at least the second packet in accordance with the kernel, where the kernel comprises a persistent kernel, and provide a second notification to the central processing unit that the at least the second packet is processed in accordance with the kernel.

Abstract: The disclosed system may include a central processing unit (CPU) interface board including a first standard port and a second standard port, a first peripheral board including a first augmented interface, the first augmented interface including first standard interface control signals and first additional interface control signals based on a first standard communication protocol, and a second peripheral board including a second augmented interface, the second augmented interface including second standard interface control signals and second additional interface control signals, the first standard interface control signals being connected to the first standard port, the second standard interface control signals being connected to the second standard port, and at least one of the first additional interface control signals being connected to a respective at least one of the second additional interface control signals. Various other methods, systems, and apparatus are also disclosed.

Abstract: A method for performing initialization in a memory device, the associated memory device and the controller thereof, and an associated electronic device are provided. The method may include: after a non-volatile (NV) memory within the memory device is powered on, searching for an empty-memory indicator in the NV memory, wherein the empty-memory indicator is applicable to determining whether the NV memory is empty; and according to whether the empty-memory indicator is found or not, selectively skipping or performing a program code search in the NV memory, to complete an initialization process, wherein the initialization process includes at least one initial setting of the memory device, and if the empty-memory indicator is found, the program code search is skipped, otherwise, the program code search is performed.

Abstract: A method includes providing a device with transmitter parameters set to default factory values. The method also includes receiving, in the device, one or more write commands with test data patterns, and executing, in the device, the one or more write commands to store the test data patterns on a non-transitory data storage medium of the device. The method further includes receiving, in the device, one or more read commands for the test data patterns, and reading the test data patterns from the non-transitory data storage medium. The read test data patterns are communicated by a signal that is sent via the device transmitter. A command instructing the device to update the transmitter parameters values is received, in the device, when a device transmitter signal integrity for the signal communication is below a predetermined threshold.

Abstract: A system that incorporates the subject disclosure may include, for example, a method that includes identifying a plurality of devices associated with a computing device, identifying status information from each device of the plurality of devices, and identifying presentation features for each device of the plurality of devices. The method further includes receiving presentation information indicating a setting to present first status information from a first device of the plurality of devices via a selected device of the plurality of devices, wherein the first status is presented on the selected device by a selected presentation feature of the selected device. Additional embodiments are disclosed.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

Abstract: A production host for hosting virtual machines includes a persistent storage and a production agent. The persistent storage stores virtual machine data of the virtual machines. The production agent obtains a dynamic backup generation rule for the virtual machines; for a predetermined period of time after obtaining the dynamic backup generate rule: generates first backups of the virtual machines based on the dynamic backup generate rule; and identifies a change rate of the virtual machine data; after the predetermined period of time, obtain a prediction-based backup generation rule that is based on the change rate of the virtual machine data over the predetermined period of time; and generates second backups of the virtual machines based on the prediction-based backup generation rule.

Abstract: A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.

Abstract: A first storage device capable of performing peer-to-peer communications with a second storage device includes a first submission queue for storing a first operation code; a first completion queue for storing a first indication signal; and a first controller configured to, read the first operation code stored in the first submission queue, create a command including a second operation code based on the first operation code, issue the command to the second storage device, and receive and processes a second completion signal transmitted from the second storage device.

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.