Abstract: A semiconductor memory includes electrode structures that each includes horizontal electrodes stacked on each other a substrate, vertical electrodes between the electrode structures and extending along the horizontal electrodes, first contacts connected to the horizontal electrodes at end portions of the electrode structures, second contacts connected to upper portions of the vertical electrodes, and a first interconnection structure connected to top surfaces of the second contacts. The first interconnection structure includes first and second sub-interconnection lines. The sub-interconnection lines extend in a first direction and contact the top surfaces of the second contacts. The second sub-interconnection lines extended in a second direction crossing the first direction and contact the first sub-interconnection lines.

Abstract: An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.

Abstract: A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of sacrificial layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of sacrificial layers is nominally proportional to a width of the channel structure at the same depth. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.

Abstract: A light emitting element includes: a substrate; a base layer disposed on the substrate; at least one rod-shaped light emitting portion comprising: a first conductivity type semiconductor rod disposed on the base layer and having a plurality of side surfaces arranged to form a polygonal column shape, an active layer formed of a semiconductor and covering the side surfaces of the first conductivity type semiconductor rod, and a second conductive type semiconductor layer covering the active layer. The active layer includes a plurality of well layers respectively disposed over at least two adjacent side surfaces among the plurality of side surfaces of the first conductivity type semiconductor rod. Adjacent well layers among the plurality of well layers are separated from each other along a ridge line where the at least two adjacent side surfaces are in contact with each other.

Abstract: Embodiments described herein comprise micro light emitting diodes (LEDs) and methods of forming such micro LEDs. In an embodiment, a nanowire LED comprises a nanowire core that includes GaN, an active layer shell around the nanowire core, where the active layer shell includes InGaN, a cladding layer shell around the active layer shell, where the cladding layer comprises p-type GaN, a conductive layer over the cladding layer, and a spacer surrounding the conductive layer. In an embodiment, a refractive index of the spacer is less than a refractive index of the cladding layer shell.

Abstract: A nonvolatile memory device and a method of fabricating a nonvolatile memory device, the device including a substrate; a first mold structure on the substrate, the first mold structure including a plurality of first mold insulation films and a plurality of first gate electrodes, which are alternately stacked; a channel structure that penetrates the first mold structure and intersects the plurality of first gate electrodes; and at least one insulation filler that intersects the plurality of first mold insulation films and the plurality of the first gate electrodes, wherein the first mold structure is electrically separated by a word line cutting region extending in a first direction such that the first mold structure includes a first block region and a second block region, and the at least one insulation filler is in the word line cutting region and connects the first block region and the second block region.

Abstract: A microelectronic device comprises a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulating structures, a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers, conductive contact structures on the steps of the staircase structure, support pillar structures laterally offset in at least a first direction from the conductive contact structures and extending through the stack structure, and bridge structures comprising an electrically insulating material extending vertically through at least a portion of the stack structure and between at least some adjacent support pillar structures of the support pillar structures. Related memory devices, electronic systems, and methods are also described.

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: A method for fabricating a memory device includes providing an initial semiconductor structure, including a base substrate, a stack structure of interlayer dielectric layers and first sacrificial layers; a channel trench formed through the stack structure. The method includes removing a portion of each first sacrificial layer from the channel trench to form a trapping-layer trench; forming a second sacrificial layer in the trapping-layer trench; forming a charge trapping film to fill the trapping-layer trench; and removing a portion of the charge trapping film from the channel trench to form a charge trapping layer; forming a tunneling layer and a channel layer on the sidewalls of the channel trench; removing the first sacrificial layers and the second sacrificial layer; forming a blocking layer on the charge trapping layer; and forming gate structures, in contact with the tunneling layer, between adjacent interlayer dielectric layers.

Abstract: A display device includes a substrate, a plurality of white light-emitting units, and a color filter layer. The white light-emitting units are arranged on the substrate at intervals, and the white light-emitting units are chip scale package (CSP). The color filter layer is above the white light-emitting units. Each of the white light-emitting units includes a light-emitting diode chip and a wavelength conversion film. The wavelength conversion film directly covers a top surface and side surfaces of the light-emitting diode chip, and the wavelength conversion film converts light emitted by the light-emitting diode chip into white light.

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, a source structure, and a support structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure includes a plurality of source portions and extending in the memory stack. The support structure is between adjacent ones of the source portions and has a plurality of interleaved conductor portions and insulating portions. A top one of the conductor portions is in contact with a top one of the conductor layers. Adjacent ones of the source portions are conductively connected to one another.

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.

Abstract: A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.