Abstract: The present invention provides a polarization separation element comprising a first array of prisms having a wedge-shaped cross-section, and a second array of prisms also having a wedge-shaped cross section. One of the prism arrays is an array of birefringent prisms. The present invention also provides a polarization conversion system having a polarization separation element of the above type for directing light having a first polarization in a first direction and for directing light having a second polarization different from the first polarization in a second direction different from the first direction; and one or more polarization conversion elements for converting light having the first and second polarizations to light having a substantially common output polarization. The polarization conversion system of the invention is suitable for use in a projection display system.

Abstract: A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.

Abstract: A bipolar transistor of type NPN has an active region at the surface of the component, which is surrounded, as seen along the surface of the component, in the conventional way by thick field oxide areas. The active region is partly covered by an electrically isolating surface layer, preferably comprising a nitride layer. A base region in the active region is defined by a well-defined opening, which is lithographically produced, in the electrically isolating surface layer. For a bipolar lateral transistor of type PNP, which instead has emitter and collector regions surrounded by such thick field oxide areas, the emitter and collector regions can in the corresponding way be defined by a lithographically defined opening in an electrically isolating surface layer. Owing to the well defined openings the base-collector capacitance and the emitter-collector capacitance respectively can be reduced in these cases, what results in better high frequency characteristics of the transistors.

Abstract: A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

Abstract: A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.

Abstract: A method for forming wafer level package that has a serpentine-shaped electrode formed along a scribe line in-between two adjacent IC dies and the package formed are disclosed. In the method, each of the I/O redistribution lines connecting from an I/O redistribution pad is connected to a serpentine-shaped electrode for providing electrical communication during a subsequent electro-deposition process for forming a solder bump on the corresponding I/O redistribution pad. During a dicing operation of the wafer level package, a single cut through the center of the serpentine-shaped electrode can effect severance of all IC dies without possibility of any inter-die shorting or intra-die shorting.

Abstract: A semiconductor device and a method for forming the same. The semiconductor device comprises an insulating or semiconductor substrate, a thermally-contractive insulating film which is formed on said substrate and provided with grooves, and a semiconductor film which is formed on the thermally-contractive insulating film and divided in an islandish form through the grooves. The thermally-contractive insulating film is contracted in a heat process after the semiconductor film is formed.

Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area o

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises a first spacer and a second spacer situated on the top surface of the base. The heterojunction bipolar transistor further comprises an intermediate oxide layer situated on the first and second oxide spacers. The heterojunction bipolar transistor further comprises an amorphous layer situated on the intermediate oxide layer. The heterojunction bipolar transistor further comprises an antireflective coating layer on the amorphous layer. The heterojunction bipolar transistor further comprises an emitter window opening situated between the first and second spacers, where the emitter window opening is defined by the top surface of the base, the first and second spacers, the intermediate oxide layer, the amorphous layer, and the antireflective coating layer.

Abstract: A bipolar device hardened against single event upset includes a voltage source, a substrate, and a surface contact. The substrate includes a first collector region, a first base region and a first emitter region. The first collector region has a first collector voltage and a first voltage threshold. The first voltage threshold is the voltage at which a bipolar device connected to the first collector or first emitter becomes upset. When the first collector voltage drops below the first voltage threshold, the attached bipolar device becomes upset. The first base region is adjacent to the first collector region and the first emitter region is adjacent to the first base region. The surface contact is disposed on the substrate and is coupled to a voltage bias generated by the voltage source. The voltage bias is greater then the first voltage threshold so that the first collector voltage is prevented from dropping below the first voltage threshold due to energetic particle induced charge.

Abstract: A liquid crystal display unit in which external vibration or impact is prevented from being applied directly to a housing member through mounting screws for fixing the liquid crystal display unit to an outer casing, so that the display quality of the display image displayed on a liquid crystal display device is improved. In a liquid crystal display unit having a backlight unit, mounting members having threaded holes into which mounting screws for fixing the liquid crystal display unit to an outer casing are screwed are provided between a side wall of a housing member of the backlight unit and a side wall of a frame member. Each of the mounting members is constituted by a first side and a second side. The first side has threaded holes and extends along the side wall of the housing member. The second side is fixed to the housing member.

Abstract: A process for making surface mountable electrical devices includes the steps of laminating two PTC sheets, two inner metal foil sheets, and two outer metal foil sheets to form a laminate such that the inner metal foil sheets are sandwiched between the PTC sheets and overlap each other and that the PTC sheets are bonded to each other, forming patterns of slits in the outer metal foil sheets, forming bores in the laminate along cutting lines, forming conductive transverse layers in interiors of the bores, and cutting the laminate along the cutting lines.

Abstract: A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.

Abstract: A semiconductor device is produced by forming a gate electrode on a semiconductor substrate, and by then forming source/drain regions by an ion implantation using the gate electrode as a mask. A suicide film is formed on at least the surface of the gate electrode. In one aspect of the invention, the ion implantation is performed by controlling a tungsten dose in a range from 0 to 5×109 atom/cm2. In another aspect of the invention, the ion implantation is performed by controlling tungsten concentration in the gate electrode ion to fall in a range from 0 to 3×1014 atom/cm3.

Abstract: In a process for patterning both sides of a double-sided HTS thin film wafer with the patterns in close registration, the first side is patterned with at least one reference mark and the second side is patterned with at least one aperture which permits alignment of the reference mark from the already applied pattern on the first side preferably to a similar reference mark on the yet to be applied patterns on the second side, such that the patterns can be aligned in close registration, using microcopic viewing techniques if necessary.

Abstract: Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: A fluid-jet printhead has a substrate on which at least one layer defining a fluid chamber for ejecting fluid is applied. The printhead includes an elevation layer disposed on the substrate and aligned with the fluid chamber. The printhead also includes a resistive layer disposed between the elevation layer and the substrate wherein the resistive layer has a smooth planer surface interfacing with the resistive layer.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: A method of manufacturing a semiconductor device comprising a poly-emitter transistor (1) and a capacitor (2). A base electrode (14), a first electrode (16, 37) and an emitter window (18) are formed at the same time in a first polysilicon layer (13) covered with an insulating layer (25). Subsequently, the side walls of the electrodes (20, 39) and the wall (23) of the emitter window are covered at the same time with insulating spacers (22, 44) by depositing a layer of an insulating material, followed by an anisotropic etching process. The base (8) of the transistor is formed by ion implantation. The emitter (9) is formed by diffusion, from an emitter electrode (30) formed in a second polysilicon layer. Preferably, the first electrode of the capacitor consists of mutually connected strips (37).