Patents Examined by Christy L. Novacek
  • Patent number: 7888225
    Abstract: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Alfred Haeusler
  • Patent number: 7883949
    Abstract: Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: February 8, 2011
    Assignee: Cree, Inc
    Inventors: Mrinal Kanti Das, Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 7879636
    Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 1, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaki Ueno, Yusuke Yoshizumi, Takao Nakamura
  • Patent number: 7879685
    Abstract: Methods for forming a patterned layer from common layer in a photovoltaic application are provided. The patterned layer is configured to form one or more portions of one or more solar cells on a rigid substrate. A first pass is made with a first laser beam over an area on the common layer. A second pass is made with a second laser beam over approximately the same area on the common layer. The first pass provides a first level of electrical isolation between a first portion and a second portion of the common layer. The second pass provides a second level of electrical isolation between the first portion and the second portion of the common layer. The second level of electrical isolation is greater than the first level of electrical isolation.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: February 1, 2011
    Assignee: Solyndra, Inc.
    Inventors: Erel Milshtein, Benyamin Buller
  • Patent number: 7875977
    Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 25, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Juergen Holz
  • Patent number: 7875500
    Abstract: The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing tape integrated type adhesive sheet formed by lamination of the adhesive sheet and a dicing tape; and a method of producing a semiconductor device using them. In order to achieve this object, the invention is characterized by specifying the breaking strength, breaking elongation, and elastic modulus of the adhesive sheet in particular numerical ranges.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: January 25, 2011
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Teiichi Inada, Michio Mashino, Michio Uruno
  • Patent number: 7871900
    Abstract: A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: January 18, 2011
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Konstantin Bourdelle, Nguyet-Phuong Nguyen, Walter Schwarzenbach
  • Patent number: 7867827
    Abstract: A physical quantity sensor is constituted using a lead frame having at least one stage and a plurality of leads whose bases are arranged in the same plane, wherein at least one physical quantity sensor chip having a plurality of electrode pads is mounted on the stage and is inclined so that the electrode pads are disposed in the inclination direction and are connected to the leads by use of wires whose lengths substantially match distances between the electrode pads and leads. This prevents the leads and wires from being unexpectedly broken, and it is possible to avoid the occurrence of separation of the leads from the physical quantity sensor chip. In addition, the tip ends of the leads are disposed along the surface of the inclined stage before wire bonding; hence, it is possible to easily connect the tip ends of the leads to the physical quantity sensor chip.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 11, 2011
    Assignee: Yamaha Corporation
    Inventors: Kenichi Shirasaka, Masayoshi Omura
  • Patent number: 7867814
    Abstract: A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: January 11, 2011
    Assignee: Fujitsu Limited
    Inventors: Mizuhisa Nihei, Hiroyasu Kawano
  • Patent number: 7863170
    Abstract: A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried zone, a second zone having a second conductivity type that is different from the first conductivity type and above the first zone, and a third zone having the first conductivity type that is above the second zone. The buried zone includes first and second implantation regions that are formed via first and second implantations that are performed using a mask. The buried zone, the first zone, the second zone and the third zone are parts of a first transistor structure.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: January 4, 2011
    Assignee: Austriamicrosystems AG
    Inventors: Georg Röhrer, Bernard Löffler, Jochen Kraft
  • Patent number: 7846767
    Abstract: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD device is provided that includes etching depressions into an etch surface of a semiconductor substrate to a uniform depth, depositing a diamond layer onto the etch surface to form diamond-filled depressions, and thinning the semiconductor substrate at a thinning surface opposite the etch surface until the diamond filled depressions are exposed, thus forming a semiconductor device having a thickness substantially equal to the uniform depth.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: December 7, 2010
    Inventor: Chien-Min Sung
  • Patent number: 7847364
    Abstract: Apparatus including flexible line extending along a length. Flexible line includes first charge carrier-transporting body, photosensitive body over first charge carrier-transporting body, and second charge carrier-transporting body over photosensitive body. Each of first and second charge carrier-transporting bodies and photosensitive body extend along at least part of length of flexible line. Photosensitive body is capable of near-infrared or visible light-induced generation of charge carrier pairs. Second charge carrier-transporting body is at least semi-transparent to near-infrared light or visible light.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: December 7, 2010
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Gang Chen, Ashok J. Maliakal, Oleg Mitrofanov, Ronen Rapaport, Nikolai Zhitenev
  • Patent number: 7842599
    Abstract: A method for forming solder bumps on an electronic component. Providing a transfer substrate having a plurality of solder balls, disposing the transfer substrate on the surface of the electronic component, heating to reflow the solder balls onto the electronic component; and removing the sacrificial substrate. The transfer substrate may comprise a sacrificial film and a metal layer patterned with a mask which is used to form solder balls on the transfer substrate. Or, the transfer substrate may comprise a sheet of material having solder balls embedded at least partially in the sheet. A method of aligning a part being bumped with a transfer substrate, using a shuttle mechanism and an alignment film is disclosed.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: November 30, 2010
    Assignee: WSTP, LLC
    Inventor: John Mackay
  • Patent number: 7838354
    Abstract: By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: November 23, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Sven Mueller, Christoph Schwan
  • Patent number: 7824932
    Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: November 2, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Hideharu Kobashi, Hiroshi Maki, Masayuki Mochizuki, Yoshiaki Makita
  • Patent number: 7820471
    Abstract: A paste in which semiconductor fine grain such as titanium oxide fine grain or the like and a binder made of a polymer compound are mixed is coated onto a transparent conductive substrate and sintered, thereby forming a semiconductor layer made of the semiconductor fine grain, after that, ultraviolet rays are irradiated to the semiconductor layer and, by using a photocatalyst effect of the semiconductor fine grain, an organic substance remaining in the semiconductor layer is removed.
    Type: Grant
    Filed: December 26, 2003
    Date of Patent: October 26, 2010
    Assignee: Sony Corporation
    Inventors: Kenichi Ishibashi, Yuichi Tokita, Masahiro Morooka, Yusuke Suzuki, Kazuhiro Noda
  • Patent number: 7816244
    Abstract: A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: October 19, 2010
    Assignees: Panasonic Corporation, IMEC
    Inventors: Shigenori Hayashi, Riichiro Mitsuhashi
  • Patent number: 7816238
    Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: October 19, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Osada, Hitoshi Kasai, Keiji Ishibashi, Seiji Nakahata, Takashi Kyono, Katsushi Akita, Yoshiki Miura
  • Patent number: RE41989
    Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: December 7, 2010
    Assignee: Advantech Global, Ltd
    Inventor: Thomas Peter Brody
  • Patent number: RE42004
    Abstract: A semiconductor device of the present invention is a semiconductor memory having a charge storage film. Recesses or holes which effectively increase the capacitance of a floating gate or a memory cell capacitor are formed in the charge storage film. These recesses or holes are formed at the same time the floating gate electrode or the lower electrode of the capacitor is isolated into the form of islands. A dielectric film and a polysilicon film is formed on the isolated island floating gate electrodes or lower electrodes. These recesses or holes increase the surface area of the dielectric film and improve the write and erase characteristics of a memory cell.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: December 21, 2010
    Inventor: Fumitaka Sugaya