Abstract: Semiconductor structures may include a substrate. The structures may include a gate structure overlying the substrate and formed in a first direction across the substrate. The structures may include a fin overlying the substrate and formed in a second direction across the substrate. The second direction may be orthogonal to the first direction, and the fin may intersect the gate structure. The structures may include a source/drain material formed about the fin. The structures may include a through-contact material extending vertically above the source/drain material. The structures may include a metal material extending vertically above the through-contact material. An interface between the metal material and the through-contact material may be characterized by a non-planar profile.

Abstract: Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

Abstract: A light emitting element includes: a first conductivity type semiconductor layer; a second conductivity type semiconductor layer disposed over the first conductivity type semiconductor layer; a first electrode and a second electrode disposed over the second conductivity type semiconductor layer and spaced apart from each other; and a light emitting layer disposed over the second conductivity type semiconductor layer and, in a top view, positioned between the first electrode and the second electrode.

Abstract: A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.

Abstract: A semiconductor device includes a first dielectric layer over a substrate, the first dielectric layer including a first dielectric material extending from a first side of the first dielectric layer distal from the substrate to a second side of the first dielectric layer opposing the first side; a second dielectric layer over the first dielectric layer; a conductive line in the first dielectric layer, the conductive line including a first conductive material, an upper surface of the conductive line being closer to the substrate than an upper surface of the first dielectric layer; a metal cap in the first dielectric layer, the metal cap being over and physically connected to the conductive line, the metal cap including a second conductive material different from the first conductive material; and a via in the second dielectric layer and physically connected to the metal cap, the via including the second conductive material.

Abstract: A semiconductor device according to an embodiment includes a substrate, first and second light emitting structures disposed on the substrate, a first reflective electrode disposed on the first light emitting structure, a second reflective electrode disposed on the second light emitting structure, a connection electrode, a first electrode pad, and a second electrode pad. According to the embodiment, the first light emitting structure includes a first semiconductor layer of a first conductivity type, a first active layer disposed on the first semiconductor layer, a second semiconductor layer of a second conductivity type and disposed on the first active layer, and a first through hole provided through the second semiconductor layer and the first active layer to expose the first semiconductor layer.

Abstract: Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.

Abstract: A method of manufacturing a semiconductor package structure is provided. The method includes providing a first carrier, forming a patterned buffer layer over the first carrier, forming a first redistribution structure that includes forming a first dielectric layer on the patterned buffer layer, after an electrical testing by applying an electric signal towards the first redistribution structure, removing the first carrier, removing portions of the first dielectric layer, resulting in a patterned first dielectric layer, the patterned first dielectric layer exposing portions of the first circuit layer, removing the exposed portions of the first circuit layer, using the patterned first dielectric layer as a mask, resulting in a patterned first circuit layer, and forming an electric conductor in a recess defined by the patterned first dielectric layer and the patterned first circuit layer.

Abstract: A display device including a substrate and a plurality of pixels in a display region of the substrate. Each of the pixels includes first and second sub-pixels, and each of the first and second sub-pixels has a light emitting region for emitting light. The first sub-pixel includes a first light emitting element in the light emitting region and configured to emit visible light. The second sub-pixel includes a second light emitting element in the light emitting region and configured to emit infrared light and a light receiving element configured to receive the infrared light emitted from the second light emitting element to detect a user's touch. The second light emitting element and the light receiving element in the second sub-pixel are electrically insulated from and optically coupled to each other to form a photo-coupler.

Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

Abstract: An optoelectronic module assembly includes an optoelectronic module. The module includes: an active optoelectronic component in or on a mounting substrate, an optical sub-assembly, and a spacer disposed between the mounting substrate and the optical sub-assembly so as to establish a particular distance between the active optoelectronic component and the optical sub-assembly. The optoelectronic module assembly also includes a recessed substrate including first and second surfaces, wherein the second surface is in a plane closer to the optical sub-assembly than is the first surface. The optoelectronic module is mounted on the first surface. The second surface is for mounting other components.

Abstract: Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K, and Wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Abstract: A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure.

Abstract: A thin film transistor array substrate includes: a first conductive layer including first lines for transmitting data signals to the thin film transistors; a second conductive layer disposed on the first conductive layer and including second lines for supplying a driving voltage to the thin film transistors; a first insulating layer disposed between a semiconductor layer and the first conductive layer and including a first material layer; a second insulating layer disposed between the first conductive layer and the second conductive layer and including a second material layer having a dielectric constant greater than that of the first material layer; and a contact plug penetrating the second insulating layer and the first insulating layer, and connecting the second conductive layer to the semiconductor layer. A taper angle of the contact plug in the second material layer is greater than that of the contact plug in the first material layer.

Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

Abstract: A process for forming an electric heater comprising the steps: (a) providing a heater element and a power supply, (b) applying a layer of a copper paste onto the heater element and/or the power supply and drying the applied layer of copper paste, (c1) applying a solder agent onto the dried copper paste and appropriately arranging the heater element and the power supply such that the heater element and the power supply contact each other by means of the dried copper paste and the solder agent or (c2) appropriately arranging the heater element and the power supply such that the heater element and the power supply contact each other by means of the dried copper paste, and applying a solder agent next to the dried copper paste or (c3) if in step (b) the copper paste has been applied only onto the heater element and then dried, applying a solder agent onto the power supply and appropriately arranging the heater element and the power supply such that the heater element and the power supply contact each other by me

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a gate stack positioned on the substrate, a plurality of programmable contacts positioned on the gate stack, a pair of heavily-doped regions positioned adjacent to two sides of the gate stack and in the substrate, and a plurality of first contacts positioned on the pair of heavily-doped regions. A width of the plurality of programmable contacts is less than a width of the plurality of first contacts.

Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

Abstract: A semiconductor device includes a first stacked body comprising first conductive layers and first insulating layers interposed therebetween, a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer between the first semiconductor layer and the first conductive layers, a second stacked body comprising second conductive layers and second insulating layers interposed therebetween, and a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer between the second semiconductor layer and the second conductive layers. The first columnar portion has a first diameter, and the second columnar portion has a second diameter, and each of the plurality of first conductive layers has a first film thickness, and each of the plurality of second conductive layers has a second film thickness.