Patents Examined by Chuong A Luu
  • Patent number: 10553521
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 4, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10551650
    Abstract: A manufacturing method of a liquid crystal display device including a first substrate and a second substrate each including a flexible board, the manufacturing method includes a first step of forming the flexible board by forming, in a first region on a glass substrate, a first resin unit made of a first resin having a property of absorbing infrared light and forming, in a second region on the glass substrate, a second resin unit made of a second resin smaller in infrared absorptivity than the first resin; and a second step of, subsequent to the first step, irradiating the first resin unit with infrared light to cut a portion corresponding to the first region in the flexible board.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 4, 2020
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Makoto Yamamoto
  • Patent number: 10551342
    Abstract: Apparatus and methods are disclosed for single molecule field effect sensors having conductive channels functionalized with a single active moiety. A region of a nanostructure (e.g., such as a silicon nanowire or a carbon nanotube) provide the conductive channel. Trapped state density of the nanostructure is modified for a portion of the nanostructure in proximity with a location where the active moiety is linked to the nanostructure. In one example, the semiconductor device includes a source, a drain, a channel including a nanostructure having a modified portion with an increased trap state density, the modified portion being further functionalized with an active moiety. A gate terminal is in electrical communication with the nanostructure. As a varying electrical signal is applied to an ionic solution in contact with the nanostructure channel, changes in current observed from the semiconductor device can be used to identify composition of the analyte.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 4, 2020
    Assignee: ILLUMINA, INC.
    Inventor: Boyan Boyanov
  • Patent number: 10546749
    Abstract: Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 28, 2020
    Assignee: AKHAN Semiconductor, Inc.
    Inventor: Adam Khan
  • Patent number: 10546916
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Patent number: 10546784
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • Patent number: 10546837
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10546747
    Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 28, 2020
    Assignee: pSemi Corporation
    Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta, Simon Edward Willard
  • Patent number: 10546903
    Abstract: The present invention discloses an organic electroluminescent display panel, including a substrate; a thin film transistor formed on the substrate; a bottom electrode formed on a drain of the thin film transistor; a light-blocking layer formed on the bottom electrode, the light-blocking layer has a first through hole that exposes the bottom electrode; a pixel define layer formed on the thin film transistor, the bottom electrode, and the light-blocking layer, the pixel define layer has a second through hole, the second through hole completely exposes the first through hole; an organic electroluminescent device formed on the bottom electrode, an edge of the organic electroluminescent device is formed on the light-blocking layer; and a top electrode formed on the organic electroluminescent device. The present invention uses the light-blocking layer to block the edge of the organic electroluminescent device, thereby eliminating the non-uniform brightness of the edge of the organic electroluminescent device.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 28, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10546883
    Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hong-Beom Lee, Ji-Hoon Shin, Ho-Yong Shin
  • Patent number: 10541161
    Abstract: Provided is a substrate treating apparatus. The substrate treating apparatus comprises: a support unit provided to support the substrate and rotate the substrate; a treatment liquid nozzle for supplying the treatment liquid onto the substrate supported by the support unit; a pre-wet liquid nozzle for supplying a pre-wet liquid onto a substrate supported by the support unit; and a controller for controlling the treatment liquid nozzle and the pre-wet liquid nozzle, wherein the controller controls the treatment liquid nozzle and the pre-wet liquid nozzle to perform a pre-wet step for supplying the pre-wet liquid to the substrate, and then a treatment liquid supply step for supplying the treatment liquid to the substrate and supplying the pre-wet liquid to the substrate during the supplying the treatment liquid to the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 21, 2020
    Assignee: SEMES CO., LTD.
    Inventors: Younghun Jung, Choongki Min, Soo Hyun Cho
  • Patent number: 10541203
    Abstract: Semiconductor fuses include a semiconductor fin having a metallized region between two non-metallized regions. Conductive layers are formed on the semiconductor fin above the two non-metallized regions. A dielectric layer is formed over the metallized region, between the conductive layers.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10535629
    Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Patent number: 10535706
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Patent number: 10535606
    Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 14, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Takashi Ando, Hiroaki Niimi, Tenko Yamashita
  • Patent number: 10529707
    Abstract: A method of forming a capacitor includes the following steps. First, a substrate is provided. A dielectric layer is formed over the substrate. A first patterning process is performed to form a first contact plug through the whole thickness of the dielectric layer and a second patterning process is performed to form a second contact plug in the dielectric layer and spaced apart from the first contact plug in a pre-determined distance, wherein the first contact plug and the second contact plug are capacitively coupled.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Hsien Chen, Sheng-Yuan Hsueh, Yi-Chung Sheng, Chih-Kai Kang, Wen-Kai Lin, Shu-Hung Yu
  • Patent number: 10529710
    Abstract: A method for manufacturing a semiconductor device having a local interconnect structure includes providing a semiconductor substrate having a gate on an active region, a hardmask layer on the gate, and a first dielectric layer on the gate, etching the first dielectric layer to form a first interconnect trench on the active region, forming a metal silicide layer at a bottom of the first interconnect trench, forming a first metal layer filling the first interconnect trench, forming a second dielectric layer on the gate and the first interconnect trench, etching the second dielectric layer to form a second interconnect trench in a staggered pattern relative to the first interconnect trench, etching the second dielectric layer to form a third interconnect trench, forming a second metal layer in the second interconnect trench and in the third interconnect trench to form the local interconnect structure.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 7, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Fenghua Fu, Yunchu Yu, Yihua Shen, Jian Pan
  • Patent number: 10529672
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
  • Patent number: 10522422
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Tsun Liu
  • Patent number: 10515861
    Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Fen Chen, Tsung-Ying Liu, Yeh-Hsun Fang, Bang-Yu Huang, Chui-Ya Peng