Patents Examined by Chuong A Luu
  • Patent number: 10497669
    Abstract: Disclosed is a die stack. The die stack may include a first plurality of dies and a second plurality of dies. Each of the plurality of dies may define a plurality of vias passing from a first side to a second side of the die. The plurality of dies may be stacked such that each of the plurality of vias in a first die are collinear with a respective via in a second die. At least one of the second plurality of dies may be wire bonded to at least one of the first plurality of dies.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Juan Eduardo Dominguez, Hyoung Il Kim
  • Patent number: 10497558
    Abstract: In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael T. Andreas, Jerome A. Imonigie, Prashant Raghu, Sanjeev Sapra, Ian K. McDaniel
  • Patent number: 10490701
    Abstract: An LED chip comprises: an operation substrate; a first conductive layer disposed on a functional surface of the operation substrate; a die disposed on the first conductive layer, wherein the die comprises a first semiconductor layer and a second semiconductor layer; a first electrode layer electrically connected with the first conductive layer; and a second electrode layer electrically connected with the second semiconductor layer, wherein a first isolation layer is disposed between the second electrode layer and the first conductive layer. In embodiments of the present disclosure, the first electrode layer and the second electrode layer are disposed on the bottom surface of the operation substrate, and are formed after the LED die is formed. Therefore, a dicing process and a packaging process are not required, thus, process steps are simplified and process cost is reduced, which is conducive to achieve “free packaging” technology.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 26, 2019
    Assignee: ENRAYTEK OPTOELECTRONICS CO., LTD.
    Inventors: Huiwen Xu, Zhengguo Yu, Qiming Li
  • Patent number: 10490378
    Abstract: Structures of and methods for fabricating fine-scale interconnects and fuses are disclosed. A “mushroom”-type structure with a narrow stalk supporting a wider cap can be used for fine-scale interconnects with widths on the scale of hundreds of nanometers that have low resistivity. Micro-air bridges can be introduced by omitting the stalk in sections of the interconnect, allowing the interconnect to bridge over obstacles. The mushroom-type micro-air bridge structure can also be modified to create fine-scale fuses that have low resistivity overall and sections of significantly higher resistivity where the micro-air bridges exist. The significantly higher resistivity results in preferential fusing at the micro-air bridges. Both mushroom interconnects and mushroom fuses can be fabricated using electron beam lithography.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 26, 2019
    Assignee: Facebook Technologies, LLC
    Inventor: Stephen John Holmes
  • Patent number: 10479676
    Abstract: A method for a MEMS device includes receiving a diced wafer having a plurality devices disposed upon an adhesive substrate and having an associated known good device data, removing a first set of devices from the plurality of devices from the adhesive substrate in response to the known good device data, picking and placing a first set of the devices into a plurality of sockets within a testing platform, testing the first set of integrated devices includes while physically stressing the first set of devices, providing electrical power to the first set of devices and receiving electrical response data from the first set of devices, determining a second set of devices from the first set of devices, in response to the electrical response data, picking and placing the second set of devices into a transport tape media.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: November 19, 2019
    Assignee: mCube, Inc.
    Inventors: Ben Lee, Ming Hong Kuo, Wen-Chih Chen, Wensen Tsai
  • Patent number: 10483357
    Abstract: A semiconductor device including: a semiconductor substrate having a drift region of the first conductivity type; a cathode region formed on the lower surface of the semiconductor substrate; a diode portion having the cathode region formed on the lower surface of the semiconductor substrate; the first dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and the first lead-out portion that is provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion is provided.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mutsumi Kitamura, Tohru Shirakawa
  • Patent number: 10475771
    Abstract: A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 10475925
    Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Hsin-Che Huang, Shyan-Liang Chou, Hung-Lin Shih
  • Patent number: 10468348
    Abstract: A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10468380
    Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 5, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kyong-Mo Bang
  • Patent number: 10468316
    Abstract: An electronic component mounting board includes a substrate on which an electronic component is mountable. The substrate includes a plurality of layers stacked on one another, a plurality of conductor layers located between the plurality of layers, and a recess located continuously over side surfaces of the plurality of layers. The electronic component mounting board includes an electrode located in the recess and covering an end of at least one of the plurality of conductor layers in the recess. The conductor layers contain a metal material different from a metal material contained in the electrode. The conductor layers have outer edges located inward from an outer edge of the substrate in a plan view.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: November 5, 2019
    Assignee: KYOCERA Corporation
    Inventor: Hiroki Iwamoto
  • Patent number: 10468303
    Abstract: A device chip manufacturing method includes a passivation film removing step of removing a passivation film along each division line, a wafer dividing step of performing plasma etching using a fluorine-based gas to the front side of a wafer in the condition where the passivation film is used as a mask, thereby dividing the wafer along the division lines, and a die attach film removing step of performing plasma etching using an oxygen-based gas to the front side of the wafer in the condition where the passivation film is used as a mask, thereby removing a part or the whole of a die attach film along each division line.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 5, 2019
    Assignee: DISCO CORPORATION
    Inventor: Tomotaka Tabuchi
  • Patent number: 10461175
    Abstract: A method for fabricating a TFT-containing backplate is disclosed. The method includes forming a top-gate TFT on a substrate. The top-gate TFT includes a gate insulating layer which includes a negative silicone light shielding material. A TFT-containing backplate is also disclosed.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 29, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianye Zhang, Youngsuk Song, Wei Li
  • Patent number: 10460973
    Abstract: The pressure sensitive adhesive tape for semiconductor processing of the present invention is a pressure sensitive adhesive tape for semiconductor processing, which, in a step of grinding a back face of a semiconductor wafer having a groove formed on a front face thereof or having a modified region formed therein to singulate the semiconductor wafer into semiconductor chips, is stuck on the front face of the semiconductor wafer and used, the pressure sensitive adhesive tape for semiconductor processing including a base, a buffer layer provided on one face of the base, and a pressure sensitive adhesive layer provided on the other face of the base, and having a ratio (D2/D1) of a thickness (D2) of the buffer layer to a thickness (D1) of the base of 0.7 or less and an indentation depth (X) of the front face on the buffer layer side of 2.5 ?m or less.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 29, 2019
    Assignee: LINTEC CORPORATION
    Inventors: Tomochika Tominaga, Katsuhiko Horigome
  • Patent number: 10453778
    Abstract: Structures of and methods for fabricating fine-scale interconnects are disclosed. A “mushroom”-type structure with a narrow stalk supporting a wider cap can be used for fine-scale interconnects with widths on the scale of hundreds of nanometers that have low resistivity. Micro-air bridges can be introduced by omitting the stalk in sections of the interconnect, allowing the interconnect to bridge over obstacles.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: October 22, 2019
    Assignee: Facebook Technologies, LLC
    Inventor: Stephen John Holmes
  • Patent number: 10453790
    Abstract: A semiconductor package includes: a semiconductor chip having connection pads; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface and including an insulating member and a redistribution layer formed on the insulating member and electrically connected to the connection pads; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; and a barrier layer disposed on the second surface of the connection member and including an organic layer containing fluorine.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Hwa Park, Ichiro Ogura
  • Patent number: 10446478
    Abstract: A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an underbump metallurgy (UBM) layer embedded in the passivation layer and electrically connected to the redistribution layer of the connection member, wherein the UBM layer includes a UBM pad embedded in the passivation layer, at least one plating layer disposed on the UBM pad and having side surfaces of which at least portions are covered by the UBM pad, and a UBM via penetrating through at least portions of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Ok Jeong, Dong Won Kang, Young Gwan Ko, Ik Jun Choi, Jung Soo Byun
  • Patent number: 10446443
    Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
  • Patent number: 10446470
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 15, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10446532
    Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, Jr.