Patents Examined by Chuong A Luu
  • Patent number: 10374083
    Abstract: A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10361340
    Abstract: A light emitting element includes an n-side semiconductor layer, a p-side semiconductor layer, a plurality of holes, a first p-electrode, a second p-electrode and an n-electrode. The n-side semiconductor layer has a hexagonal shape in plan view. The p-side semiconductor layer has a hexagonal shape in plan view and provided over the n-side semiconductor layer. The holes are arranged in the p-side semiconductor layer so that the n-side semiconductor layer is exposed through the plurality of holes. The first p-electrode is in contact with the p-side semiconductor layer. The second p-electrode is arranged on the first p-electrode adjacent to a corner corresponding to one of vertices of the hexagonal shape. The second p-electrode has sides that are respectively parallel to sides defining the corner in plan view. The n-electrode is arranged over the first p-electrode and is electrically connected to the n-side semiconductor layer through the plurality of holes.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 23, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Koichi Takenaga, Keiji Emura
  • Patent number: 10361319
    Abstract: An integrated circuit device includes a substrate, first and second fin active regions formed on the substrate and extending in a first direction parallel to a top surface of the substrate, a first gate structure disposed on a side surface of the first fin active region, a pair of first impurity regions respectively formed on a top portion and a bottom portion of the first fin active region, a second gate structure disposed on a side surface of the second fin active region, and a pair of second impurity regions respectively formed on a top portion or a bottom portion of the second fin active region, wherein the pair of first impurity regions vertically overlap each other, and the pair of second impurity regions do not vertically overlap each other.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Yeon-cheol Heo, Maria Toledano Luque
  • Patent number: 10361087
    Abstract: A process for manufacturing an intermetallic contact on the surface of a layer or of a substrate of oriented InxGa1-xAs material, the contact includes an Ni—InGaAs intermetallic compound, the intermetallic compound having a hexagonal crystallographic structure that may have: a first texture or a second texture formed at a second nucleation temperature above the first nucleation temperature; the process comprising the following steps: the production of nomograms defining, for a thickness of Ni deposited, the time to completely consume the initial thickness of Ni as a function of the annealing temperature, the annealing temperature being below the nucleation temperature of the second texture; the localized deposition of Ni on the surface of the InxGa1-xAs material; an annealing step applying the pair of parameters: time required/annealing temperature, deduced from the nomograms, comprising at least one temperature rise step and at least one temperature hold of the final annealing temperature.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Philippe Rodriguez, Seifeddine Zhiou, Fabrice Nemouchi, Patrice Gergaud
  • Patent number: 10351765
    Abstract: An organic electroluminescence device includes an anode, an emitting layer and a cathode, in which the emitting layer includes a first compound and a second compound, the first compound is a delayed fluorescent compound, the second compound is a fluorescent compound, an emission quantum efficiency of the first compound is 70% or less, and an ionization potential Ip1 of the first compound and an ionization potential Ip2 of the second compound satisfy a relationship of 0?Ip2?Ip1?0.8 eV.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 16, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Toshinari Ogiwara, Yuichiro Kawamura
  • Patent number: 10347560
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10347691
    Abstract: The present invention is directed to a magnetic structure, which includes a magnetic fixed layer structure formed on top of a seed layer structure. The seed layer structure includes one or more layers of a first transition metal, which may be platinum, palladium, nickel, or iridium, interleaved with one or more layers of a second transition metal, which may be tantalum, titanium, vanadium, molybdenum, chromium, tungsten, zirconium, hafnium, or niobium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first magnetic material interleaved with layers of the first transition metal. The first magnetic material may be made of cobalt.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 9, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Bing K. Yen, Huadong Gan
  • Patent number: 10340232
    Abstract: A wiring substrate includes a coil wiring and a magnetic layer that is in contact with a lower surface of the coil wiring and includes an opening extending through in a thickness-wise direction. The wiring substrate further includes a first insulation layer covering the coil wiring, an upper surface of the magnetic layer, and a wall surface of the opening and a signal wiring structure formed so that a signal of a semiconductor element, when mounted on the wiring substrate, travels through the opening of the magnetic layer. The signal wiring structure includes a first wiring portion located on an upper surface of the first insulation layer and a first via wiring located inward from the opening of the magnetic layer and connected to the first wiring portion. The magnetic layer is not in contact with the signal wiring structure.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 2, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Toshiaki Aoki, Shinji Nakazawa
  • Patent number: 10334685
    Abstract: An electroluminescent LED device comprising a hole transport layer, an electron transport layer, an active emissive layer between the hole transport layer and the electron transport layer, and carbon dots forming the active emissive layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 25, 2019
    Assignee: Board of Supervisors of Louisiana State University and Agricultural and Mechanical College
    Inventors: Weiyong Yu, Yu Zhang
  • Patent number: 10319846
    Abstract: A semiconductor structure includes a substrate, an isolation layer disposed over the substrate, a plurality of nanosheet channels, interfacial layers surrounding each of the nanosheet channels, and dielectric layers surrounding each of the interfacial layers. The plurality of nanosheet channels includes first and second sets of two or more nanosheet channels for first and second NFETs and third and fourth sets of two or more nanosheet channels for first and second PFETs. The interfacial layers surrounding the first and third sets of nanosheet channels for the first NFET and the first PFET have a first thickness, and interfacial layers surrounding the second and fourth sets of nanosheets channels for the second NFET and the second PFET have a second thickness smaller than the first thickness. The first NFET has a higher threshold voltage than the second NFET, and the first PFET has a lower threshold voltage than the second PFET.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, ChoongHyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 10319882
    Abstract: Exemplary embodiments provide a UV light emitting diode and a method of fabricating the same. The method of fabricating a UV light emitting diode includes growing a first n-type semiconductor layer including AlGaN, wherein growth of the first n-type semiconductor layer includes changing a growth pressure within a growth chamber and changing a flow rate of an n-type dopant source introduced into the growth chamber. A pressure change during growth of the first n-type semiconductor layer includes at least one cycle of a pressure increasing period and a pressure decreasing period over time, and change in flow rate of the n-type dopant source includes increasing the flow rate of the n-type dopant source in the form of at least one pulse. The UV light emitting diode fabricated by the method has excellent crystallinity.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 11, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Ki Yon Park, Jeong Hun Heo, Hwa Mok Kim, Gun Woo Han
  • Patent number: 10319848
    Abstract: A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 11, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 10312460
    Abstract: An optoelectronic device includes a flexible organic light-emitting diode having a main extension plane, a first retaining element having a first major surface formed in accordance with a bent surface, and a second retaining element, wherein the OLED is arranged between the first retaining element and the second retaining element, and the OLED is mechanically fixed by the first retaining element and/or the second retaining element such that the main extension plane of the OLED is formed in accordance with the bent surface.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 4, 2019
    Assignee: OSRAM OLED GmbH
    Inventors: Daniel Riedel, Nina Riegel, Thomas Wehlus, Arne Fleißner, Armin Heinrichsdobler, Sebastian Wittmann
  • Patent number: 10310643
    Abstract: A touch panel includes: an adhesive layer formed on a base film; a protective layer formed on the adhesive layer; a touch sensor portion formed on the protective layer; a bonding pad portion comprising a plurality of unit bonding pads formed on the protective layer as electrically connected to the touch sensor portion; and a first insulating layer formed on the protective layer to extend from a unit bonding pad while filling separation regions between the unit bonding pads. Since the deformations in the elements of the touch panel during the process of bonding the touch panel and the flexible printed circuit board are prevented, there are effects that the degradation in the performance of the touch panel is prevented, and the structural stability of the junction structure of the touch panel and the flexible printed circuit board is secured.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: June 4, 2019
    Assignee: Dongwoo Fine-Chem Co., Ltd.
    Inventors: Han Sub Ryu, Yong Soo Park, Euk Kun Yoon
  • Patent number: 10312097
    Abstract: A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a substrate; and forming a first source/drain region in the semiconductor material layer. The method may continue with forming a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region that is substantially perpendicular to the vertically orientated channel region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region. Thereafter, a gate structure is formed on the vertically orientated channel region, and a second source/drain region is formed on the vertically orientated channel region.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10312145
    Abstract: A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure and the fins. The spacer layer is recessed to form asymmetrically recessed spacers along sidewalls of each of the fins, thereby exposing a portion of each of the fins. A source/drain epitaxy is grown on the exposed portions of the plurality of fins, a first source/drain epitaxy on a first fin being asymmetrical to a second source/drain epitaxy on a second fin. A device includes a first and second fin on a substrate with a gate structure formed over the first and second fins. An epitaxy if formed over the first fin and the second fin on the same side of the gate structure, where the height of the first epitaxy is greater than the height of the second epitaxy.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10297502
    Abstract: A semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. Each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. Alternatively, the etch via is empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 21, 2019
    Assignees: X-Celeprint Limited, X-FAB Semiconductor Foundries AG
    Inventors: Christopher Andrew Bower, Ronald S. Cok, William Andrew Nevin, Gabriel Kittler
  • Patent number: 10297529
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10297560
    Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Yi-Wen Wu, Tzung-Hui Lee
  • Patent number: 10290536
    Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao