Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure dividing the fin-shaped structure into a first portion and a second portion as the SDB structure includes a bottom portion in the fin-shaped structure and a top portion on the bottom portion, a spacer around the top portion, a first epitaxial layer adjacent to one side of the top portion, and a second epitaxial layer adjacent to another side of the top portion.

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate comprising a first top surface; an isolation region disposed in the substrate; an active region surrounded by the isolation region; a gate trench disposed in the active region; a first barrier layer disposed on a portion of a sidewall of the gate trench; a first gate material disposed in the gate trench, wherein the first gate material comprises a first member surrounded by the first barrier layer and a second member extending from the first member toward the first top surface; a second barrier layer disposed on the first barrier layer and the first gate material; a second gate material disposed on the second barrier layer; and a gate insulating material disposed on the second gate material.

Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first through substrate via (TSV) disposed within a semiconductor substrate. The semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the semiconductor substrate. The semiconductor substrate comprises a first doped channel region extending from the front-side surface to the back-side surface. The first TSV is defined at least by the first doped channel region. A conductive contact overlies the back-side surface of the semiconductor substrate and comprises a first conductive layer overlying the first TSV. The first conductive layer comprises a conductive material. An upper conductive layer underlies the conductive contact. An upper surface of the upper conductive layer is aligned with the back-side surface of the semiconductor substrate. The upper conductive layer comprises a silicide of the conductive material.

Abstract: Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads.

Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

Abstract: An epitaxial LED wafer is provided and chip process is processed such that each LED chip on the epitaxial wafer can be probed by an array of probe pin and results can be stored in a database. The epitaxial wafer is then diced on an expandable tape, and a display substrate is provided with driving circuits. The tape is expanded such that a pitch of LED chips on the tape is equal to a pitch of LED chips on display substrate. An array of drop pins will collectively and selectively drop LED chips, from the tape to the display substrate, with the same specification according to the probed results in the database.

Abstract: Methods and apparatuses for slit oxide and via formation techniques are described, for example, for fabricating three dimensional memory devices that may include multiple decks of memory cells that each include memory cell stacks and associated access lines. The techniques may create an interconnect region without removing a portion of the memory cell stacks. The interconnect region may include one or more conductive vias extending through the decks of memory cells to couple the access lines with logic circuitry that may be located underneath the decks of memory cells. Further, the techniques may divide an array of memory cells into multiple subarrays of memory cells by forming trenches, which may sever the access lines. In some cases, each subarray of memory cells may be electrically isolated from other subarrays of memory cells. The techniques may reduce a total number of fabrication process steps.

Abstract: A photorelay of an embodiment includes a polyimide substrate having a first surface and a second surface on an opposite side of the polyimide substrate from the first surface, the polyimide substrate having a thickness equal to or more than 10 ?m and equal to or less than 120 ?m, an input terminal provided on the second surface, an output terminal provided on the second surface, a light receiving element provided on the first surface, a light emitting element provided on the light receiving element, and a MOSFET provided on the first surface.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: A semiconductor device that includes a through hole forming region, an insulating wall, a semiconductor substrate, a side wall insulating film, and an electric conductor. The insulating wall has an inner peripheral surface surrounding the through hole forming region. The semiconductor substrate has the insulating wall buried in one of surfaces thereof. The semiconductor substrate has a through hole whose side wall is provided outwardly from the inner peripheral surface of the insulating wall. The side wall insulating film covers the side wall of the through hole and the inner peripheral surface of the insulating wall. The electric conductor is provided in the through hole of the semiconductor substrate via the side wall insulating film.

Abstract: The present invention is directed to a perpendicular magnetic structure comprising a first seed layer including tantalum, a second seed layer deposited on top of the first seed layer and including iridium, a third seed layer deposited on top of the second seed layer, and a fourth seed layer deposited on top of the third seed layer and including chromium. The third seed layer includes one of NiFe, NiFeB, NiFeCr, CoFeB, CoFeTa, CoFeW, CoFeMo, CoFeTaB, CoFeWB, or CoFeMoB. The perpendicular magnetic structure further includes a magnetic fixed layer structure formed on top of the fourth seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane of the magnetic fixed layer structure. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The magnetic material includes cobalt. The transition metal includes one of nickel, platinum, palladium, or iridium.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A semiconductor device includes a base substrate, a detection device provided on the base substrate and including a detector, a first connector electrically connecting the base substrate and the detection device, and a resin package provided on the base substrate and embedded with the detection device and the first connector. The resin package includes an exposure hole exposing the detector of the detection device to the outside, and a concave-convex portion.

Abstract: A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench.