Abstract: An electronic device has an activation function functional block that implements an activation function. During operation, the activation function functional block receives an input including a plurality of bits representing a numerical value. The activation function functional block then determines a range from among a plurality of ranges into which the input falls, each range including a separate portion of possible numerical values of the input. The activation function functional block next generates a result of a linear function associated with the range. Generating the result includes using a separate linear function that is associated with each range in the plurality of ranges to approximate results of the activation function within that range.

Abstract: Techniques described herein may be utilized to implement methods and systems for lossless compression and serialization of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialization and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

Abstract: Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

Abstract: Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.

Abstract: Random number generators include a thermal optical source and detector configured to produce random numbers based on quantum-optical intensity fluctuations. An optical flux is detected, and signals proportional to optical intensity and a delayed optical intensity are combined. The combined signals can be electrical signals or optical signals, and the optical source is selected so as to have low coherence over a predetermined range of delay times. Balanced optical detectors can be used to reduce common mode noise, and in some examples, the optical flux is directed to only one of a pair of balanced detectors.

Abstract: A random code generator includes a power source, a sensing circuit, a first memory cell and a second memory cell. A first terminal of the first memory cell is connected with the power source. A second terminal of the first memory cell is connected with the sensing circuit. A first terminal of the second memory cell is connected with the power source. A second terminal of the second memory cell is connected with the sensing circuit. The power source provides a supplying voltage to both the first memory cell and the second memory cell during an enrollment. A random code is then determined according to the resistance difference between the first memory cell and the second memory cell after the enrollment.

Abstract: A device for signal processing includes a signal input, a control input, and a CIC filter of an nth order for filtering the input signal. The CIC filter includes n integrators, which are disposed one behind the other and include a memory in each case, and n is greater than one. For each of n?1 first integrators, the device includes an associated correction calculator for correcting an integration error using at least one signal value stored in the memory of the respective first integrator. The device transmits these stored signal values in response to the control signal to the associated correction calculators and to delete the memory of the remaining last integrator. Either the memories of the n?1 first integrators are also deleted, or the device includes a further correction calculator and the signal values are transmitted in response to the control signal also to the further correction calculator.

Abstract: Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

Abstract: Provided are a security processor for performing a remainder operation by using a random number and an operating method of the security processor. The security processor includes a random number generator configured to generate a first random number; a modular calculator configured to generate a first random operand based on first data and the first random number and generate output data through a remainder operation on the first random operand, wherein a result value of the remainder operation on the first input data is identical to a result value of the remainder operation on the first random operand.

Abstract: Electric charges depending on values of N+ electric signals and values of corresponding positive loads are held in first capture-and-storage circuitry. Electric charges having a size depending on values of (N?N+) electric signals and corresponding absolute values of negative loads are held in second capture-and-storage circuitry. A sum of N+ multiplied values obtained by multiplying each of the positive loads by each of the values of the N+ electric signals is calculated when a voltage held in the first capture-and-storage circuitry reaches a first threshold. A sum of (N?N+) multiplied values obtained by multiplying each of the absolute values by each of the values of the (N?N+) electric signals is calculated when a voltage held in the second capture-and-storage circuitry reaches a second threshold A sum of N multiplied values is obtained by subtracting the sum of (N?N+) multiplied values from the sum of N+ multiplied values.

Abstract: A convolutional layer in a convolutional neural network uses a predetermined horizontal input stride and a predetermined vertical input stride that are greater than 1 while the hardware forming the convolutional layer operates using an input stride of 1. Each original weight kernel of a plurality of sets of original weight kernels is subdivided based on the predetermined horizontal and vertical input strides to form a set of a plurality of sub-kernels for each set of original weight kernels. Each of a plurality of IFMs is subdivided based on the predetermined horizontal and vertical input strides to form a plurality of sub-maps. Each sub-map is convolved by the corresponding sub-kernel for a set of original weight kernels using an input stride of 1. A convolved result of each sub-map and the corresponding sub-kernel is summed to form an output feature map.

Abstract: Methods, systems, and apparatus, including a system for transforming sparse elements to a dense matrix. The system is configured to receive a request for an output matrix based on sparse elements including sparse elements associated with a first dense matrix and sparse elements associated with a second dense matrix; obtain the sparse elements associated with the first dense matrix fetched by a first group of sparse element access units; obtain the sparse elements associated with the second dense matrix fetched by a second group of sparse element access units; and transform the sparse elements associated with the first dense matrix and the sparse elements associated with the second dense matrix to generate the output dense matrix that includes the sparse elements associated with the first dense matrix and the sparse elements associated with the second dense matrix.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: A system and methods for designing single-stage hardware sorting blocks, and further using the single-stage hardware sorting blocks to reduce the number of stages in multistage sorting processes, or to define multiway merge sorting networks.

Abstract: A matrix computation unit includes a systolic array of cells arranged along a first and second dimension, in which the systolic array of cells includes a first multiple of cells, each cell of the first multiple of cells including: a weight register configured to store a weight input; multiple activation registers, each activation register of the multiple activation registers configured to store a corresponding activation input; multiplexer circuitry communicatively coupled to the multiple activation registers and configured to select, from the multiple activation registers, one of the activation inputs as a selected activation input; and multiplication circuitry communicatively coupled to the weight register and to the multiplexer, in which the multiplication circuitry is configured to output a product of the weight input and the selected activation input.

Abstract: Methodology to reduce the running time of any string sorting algorithm is described. In one methodology, a prefix of each string from the input unsorted string array is converted to an integer and placed in an array. The array of integers is sorted using the given sorting algorithm. In subsequent methodology, the characters of the string prefix are placed in a record structure and stored in an array of character records. The array of character records is sorted using the given sorting algorithm. The input unsorted array of strings is then sorted using either the sorted array of integers or character records as a reference. Both methodologies showed performance improvements when running in sequential mode only. Therefore, parallel data sort methodology (PDS) was introduced allowing sorting algorithms to sort data in parallel, and its implementation made the two methodologies execute much faster in parallel mode.

Abstract: A vehicular arithmetic operation processing device that is mounted in a vehicle having a communication function of communicating with an outside of the vehicle and the vehicular arithmetic operation processing device includes an electronic control unit. The electronic control unit is configured to: perform an arithmetic operation for an arithmetic operation task, output a result of the arithmetic operation, and receive an arithmetic operation task from the outside of the vehicle by using the communication function when an amount of arithmetic operations performed in the vehicular arithmetic operation processing device is equal to or less than a predetermined first value; and transmit an arithmetic operation task to the outside of the vehicle by using the communication function when the amount of arithmetic operations which are performed in the vehicular arithmetic operation processing device is equal to or greater than a predetermined second value.

Abstract: An electronic control device includes: a logic circuit for reconfiguring a plurality of arithmetic circuits including a first circuit and a second circuit; a reconfiguration controller that reconfigures the arithmetic circuits and checks the reconfigured arithmetic circuits based on reconfiguration commands; and a process controller that transmits the reconfiguration commands to the reconfiguration controller and instructs the arithmetic unit to execute operations, in which when a first reconfiguration command is received, the reconfiguration controller reconfigures and checks the first circuit, when the check of the first circuit by the reconfiguration controller is completed, the process controller instructs the first circuit to execute an operation, the process controller transmits a second reconfiguration command to the reconfiguration controller and instructs the reconfiguration controller to start to reconfigure the second circuit until the execution of a predetermined process of the first circuit is co

Abstract: An arithmetic processing apparatus includes an arithmetic circuit configured to perform an arithmetic operation on data having a first data width and perform an instruction in parallel on each element of data having a second data width, and a cache memory configured to store data, wherein the cache memory includes a tag circuit storing tags for respective ways, a data circuit storing data for the respective ways, a determination circuit that determines a type of an instruction with respect to whether data accessed by the instruction has the first data width or the second data width, and a control circuit that performs either a first pipeline operation where the tag circuit and the data circuit are accessed in parallel or a second pipeline operation where the data circuit is accessed in accordance with a tag result after accessing the tag circuit, based on a result determined by the determination circuit.

Abstract: A functional unit for a data processor comprises an input register to store a variable X; a first circuit, having an input connected to the input register and an output, to generate a value eX on its output; a second circuit, having an input connected to the input register and an output, to generate an output which is a value (tan h(X/2)+1)/2 on its output; a comparator, having an input connected to the input register and an output, to generate a line on its output based on a comparison between X and a constant; and a selector to select between inputs connected to the outputs of the first circuit and the second circuit, in response to the output of the comparator, and provide an output representing a value sigmoid(X).