Abstract: A digital signal processor is designed to channelize an input signal, and includes a channelizer circuit and a plurality of tuning modules. The channelizer circuit is designed to receive an input signal having a first bandwidth and to channelize the input signal into a first set of channels each having a bandwidth smaller than the first bandwidth as a first output signal and to channelize the input signal into a second set of channels having a bandwidth smaller than the first bandwidth as a second output signal. The plurality of tuning modules are designed to receive one or more channels from the first output signal or the second output signal and to further downsample the one or more channels to a user-defined bandwidth at a user-defined center frequency. Each of the plurality of tuning modules include a plurality of FIR filter blocks and a memory having a plurality of FIR filter coefficients.

Abstract: In a system for improving performance of tensor-based computations and for minimizing the associated memory usage, computations associated with different non-zero tensor values are performed while exploiting an overlap between the respective index tuples of those non-zero values. While performing computations associated with a selected mode, when an index corresponding to a particular mode in a current index tuple is the same as the corresponding index from another, previously processed index tuple, the value already stored in a buffer corresponding to that particular mode is reused either wholly or in part, minimizing the processor usage and improving performance. Certain matrix operations may be iterated more than once so as to avoid the need to store a large partial result obtained from those operations. The performance overhead of the repeated operations is not significant, but the reduction in memory usage is.

Abstract: A correlithm object processing system includes a reference table that stores a plurality of correlithm objects, a demultiplexer configured to split a particular one of the plurality of correlithm objects into a first portion of the binary string and a second portion of the binary string, and a multiplexer communicatively coupled to the demultiplexer by at least first and second communication channels. The multiplexer receives the first and second portions of the particular correlithm object over the first and second communication channels, respectively, and combines the first and second portions into a received correlithm object. A node communicatively coupled to the multiplexer node determines distances between the received correlithm object and each of the plurality of correlithm objects stored in the reference table, identifies one of the plurality of correlithm objects from the reference table with the shortest distance, and outputs the identified correlithm object.

Abstract: A computer implemented method for performing fault tolerant numerical linear algebra computation task consisting of calculation steps that include at least classic or fast matrix multiplication, according to which, a controller splits the task among P processors, which operate in parallel. Additional processors are assigned according to execution and resources parameters, which are also used to select a slice-coded recovery algorithm or a posterior-recovery algorithm for executing the task. Pipelined-reduce operations are used to generate error correcting codes to protect the input blocks and outer products from faults. Upon detecting faults in one or more processors, if the slice-coded recovery algorithm has been selected, a slice-coded recovery algorithm is executed to recover lost input blocks and outer products that.

Abstract: A DC-removing cascaded integrator-comb (CIC) filter circuit (40) includes N series-coupled integrator stages (401-405), a rate changer (406), and N series-coupled comb stages (407-411) which are configured to receive a CIC filter digital input signal and to generate a CIC filter digital output signal, wherein the N integrator stages include a first integrator stage (401) which includes a summation element (41) having first input for receiving a first input signal, a second input for receiving a second input signal, and an output coupled through a feedback delay element (42) to a multiplier element (43) which multiplies a DC-removing filter coefficient with an output of the feedback delay element to generate a product output that is provided to the second input of the summation element (41), thereby embedding a DC-removing filter in the N series-coupled integrator stages.

Abstract: An automated system is provided. Examples of automated systems include processors for calculation which implement a secure boot process based on the plurality of numbers; chip cards for authentication; telecommunication equipment; programmable logic controllers, control devices for railways, etc. The operation is controlled depending on whether a sequential test for randomness of a plurality of numbers from a physical random number generator is marked as failed. This has the advantage that an online-test for integrity of the plurality of numbers is possible at a high accuracy and low latency.

Abstract: A batched Cholesky decomposition method, system, and non-transitory computer readable medium for a Graphics Processing Unit (GPU), include mirroring a second problem matrix of a second problem to a first problem matrix of a first problem as paired matrices and shifting the second problem matrix by N+1 and combining the first problem matrix and the mirrored second problem matrix into one matrix of (N+1)×N, where the first problem shared memory comprises regular intervals, where the second problem shared memory is continuous, and where the GPU performs batched dense Cholesky decomposition with the one matrix from the combining to accelerate the Cholesky decomposition.

Abstract: A device configured to emulate a correlithm object processing system includes a memory that stores a node table that identifies a plurality of source correlithm objects and a plurality of corresponding target correlithm objects. The system further includes a node coupled to the memory and configured to receive an input correlithm object, identify a source correlithm object from the node table with the shortest n-dimensional distance to the input correlithm object, and identify a first target correlithm object from the node table linked with the identified source correlithm object. The node further generates a second target correlithm object that is offset in n-dimensional space from the first target correlithm object by the distance between the input correlithm object and the identified source correlithm object. The node outputs the second target correlithm object.

Abstract: A device configured to emulate a correlithm object system includes a memory that stores a sensor table. The sensor table identifies a plurality of real-world value entries and a plurality of corresponding input correlithm objects. A sensor receives a first input signal associated with a first timestamp, the first input signal representing a first real-world value entry in the sensor table. The sensor identifies a first input correlithm object in the sensor table linked with the first real-world value entry and outputs the first input correlithm object. The memory further stores a sensor output table that identifies the first real-world value entry associated with the first input correlithm object and the first timestamp.

Abstract: A computer-implemented method comprising: from each of multiple trials, obtaining a respective series of observations y(t) of a subject over time t; using a variational auto encoder to model an ordinary differential equation, ODE, wherein the variational auto encoder comprises an encoder for encoding the observations into a latent vector z and a decoder for decoding the latent vector, the encoder comprising a first neural network and the decoder comprising one or more second neural networks, wherein the ODE as modelled by the decoder has a state x(t) representing one or more physical properties of the subject which result in the observations y, and the decoder models a rate of change of x with respect to time t as a function f of at least x and z: dx/dt=f(x, z); and operating the variational auto encoder to learn the function f based on the obtained observations y.

Abstract: Methods, apparatus, systems and articles of manufacture to perform dot product calculations using sparse vectors are disclosed. An example dot product calculator includes a first logic AND gate to perform a first logic AND operation with a first input vector and a second input vector, the first logic AND gate to output a control vector; a second logic AND gate to perform a second logic AND operation with a difference vector and an inverse of the control vector, the second logic AND gate to output a mask vector; a third logic AND gate to output a first vector; a first counter to generate a first ones count based on a first total number of ones of the first vector; a fourth logic AND gate to output a second vector; a second counter to generate a second ones count; and a multiplier to generate a product.

Abstract: The disclosed computer-implemented method may include receiving an input value and a floating-point scaling factor and determining (1) an integer scaling factor based on the floating-point scaling factor, (2) a pre-scaling adjustment value representative of a number of places by which to shift a binary representation of the input value prior to a scaling operation, and (3) a post-scaling adjustment value representative of a number of places by which to shift the binary representation of the input value following the scaling operation. The method may further include calculating a scaled result value by (1) shifting rightwards the binary representation of the input value by the pre-scaling adjustment value, (2) scaling the shifted binary representation of the input value by the integer scaling factor, and (3) shifting rightwards the shifted and scaled binary value by the post-scaling adjustment value. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems, methods, and devices for enhancing performance/efficiency of soft multiplier implementations are provided. More specifically, a method to implement soft multipliers with a high radix subset code architecture is provided. The techniques provided herein result in smaller multipliers that consume less area, improve packing, consume less power, and improve routing options on an integrated circuit.

Abstract: A device configured to emulate a correlithm object system includes a memory configured to store a plurality of correlithm objects associated with different levels of string correlithm objects. The device further includes a node and an actor coupled to the memory and configured to receive an input correlithm object representing a task to be performed and output real-world data based on a comparison in n-dimensional space between the input correlithm object and one or more of the different levels of string correlithm objects.

Abstract: Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

Abstract: An accelerating device includes a signal detector that converts a first input signal and a second input signal into a first converted input signal and a second converted input signal, respectively, and that generates a final zero-value flag signal, a first one-value flag signal, and a second one-value flag signal. The accelerating device further includes a processing element (PE) that processes the first converted input signal and the second converted input signal based on the final zero-value flag signal, the first one-value flag signal, and the second one-value flag signal and that skips a first arithmetic operation and a second arithmetic operation when the final zero-value flag signal has a first value. The first value of the final zero-value flag signal indicates that the first input signal, or the second input signal, or both have a value of 0.

Abstract: A device configured to emulate a string correlithm object velocity detector includes a memory that stores a first string correlithm object comprising a plurality of sub-string correlithm objects. The device further includes a sensor coupled to the memory and configured to determine a time between performing data processing associated with the plurality of sub-string correlithm objects, and represent those times as correlithm objects.

Abstract: A processor can scan a portion of a vector to identify first nonzero entries. The processor can scan another portion of the vector to identify second nonzero entries. The processor can scale a portion of a matrix using the first nonzero entries to generate first intermediate elements. The processor can scale another portion of the matrix using the second nonzero entries to generate second intermediate elements. The processor can store the first intermediate elements in a first buffer and store the second intermediate elements in a second buffer. The processor can copy a subset of the first intermediate elements from the first buffer to a memory and copy a subset of the second intermediate elements from the second buffer to the memory. The subsets of first and second intermediate elements can be aggregated to generate an output vector.

Abstract: A method and apparatus is provided for implementing combinatorial hypermaps (CHYMAPS) and/or generalized combinatorial maps (G-Maps) based data representations and operations, comprising: mapping term-algebras to tree-based numbers using a fast algorithm and representing a graph of the mapping structure as a CHYMAPS using reversible numeric encoding and decoding; generating a representation of CHYMAPS in a form optimized for sub-map (sub-graph) to map (graph) isomorphism and partial matching with a general matching process; performing operations on the CHYMAPS as operations on respective numerical representations; performing compression and decompression using a three bit self-delimiting binary code; and storing and retrieving codes.

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.