Abstract: The invention comprises a method for calculating an orthogonal discrete transform on the basis of the DIT method in prescribed intermediate steps with the following steps: the data are read from a memory organized on page-for-page basis; the intermediate step prescribed by the transform is carried out; the resulting data are stored in a buffer memory; and the resulting data are written page-for-page from the buffer memory to the memory organized on a page-for-page basis. Suitable discrete orthogonal transforms are FFT, IFFT, DCT, IDCT and transforms of similar structure.

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: A system is provided for processing digital data from an array of receiver elements. The system includes an input assembly interface and a processing element. The input assembly interface is capable of providing the digital data from the array of receiver elements. The processing element, in turn, is capable of providing an impulse response, and representing the digital data and impulse response vectorized receiver matrices and vectorized response matrices, respectively. The processing element can then signal condition the digital data, without corner turning, based upon the vectorized receiver matrices and the vectorized response matrices. Once the signal conditioning output has been computed, the digital data may be further processed by a beamformer and matched filter.

Abstract: A round off mechanism maintains a mean value of the operand while rounding twos complement binary data. Positive data values are incremented at the first discard bit prior to truncation of the discard bits, as are negative data values having a one within the most significant discard bit and at least one other discard bit. The discard bits are simply truncated for all other negative data values.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: One embodiment of the present invention provides a system for finding the roots of a polynomial or a quadratic equation with interval coefficients. The system operates by receiving a representation of a polynomial equation, which can be a quadratic equation of the form F(x)=Ax2+Bx+C=0, wherein A=[AL, AU], B=[BL, BU] and C=[CL, CU] are interval coefficients. Next, the system computes intervals containing roots of the functions F1(x), F2(x), F3(x) and F4(x), wherein F1(x)=ALx2+BLx+CL, F2(x)=AUx2+BUx+CU, F3(x)=ALx2+BUx+CL and F4(x)=AUx2+BLx+CU. The system then places the computed intervals into a list, L, and orders the computed intervals in L by their left endpoints, so that for a each entry, Si=[SiL, SiU], SiL?Si+1,L. Next, the system establishes interval roots for F(x) from the interval entries in list L.

Abstract: To perform a product-sum operation by adding third data to a product of first data and second data, a floating point multiplier first multiplies the first data by the second data, and a bit string representing a fixed-point part in the multiplication result is divided into a portion representing more significant digits in the fixed-point part and a portion representing less significant digits in the fixed-point part. Then, a floating point adder first adds less significant multiplication result data having a bit string representing the less significant digits as a fixed-point part to the third data, and then adds the addition result to more significant multiplication result data having a bit string representing the more significant digits as a fixed-point part. A rounding process is performed on the two addition results to obtain a result of the product-sum operation.

Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

Abstract: One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein the thermometer code uses m bits to represent a string of m identical consecutive digits within the string of n digits. Next, the system converts the thermometer code into a one-hot code in which only one bit has a logical one value. Finally, the system converts the one-hot code into a logarithmic code representing the number of identical consecutive digits.

Abstract: A calculator with liquid ornament includes a base, on a predetermined position of which a downward cavity is formed for detachably or fixedly receiving a hollow enclosure therein. The cavity has dimensions and shape matching with an appearance of the base, and the hollow enclosure has dimensions and shape matching with appearances of the calculator and the cavity to create an integral beauty for the calculator. The hollow enclosure is adapted to contain different types of decorative liquids and floating ornaments therein, giving the calculator a unique appearance and added value.

Abstract: A method of reducing the amount of computer memory utilized in calculating a formula on a collection of a plurality of series of data values, the method including the steps of: (a) for each data value member of at least one series of the collection, determining the size of a window of data values required to calculate the formula; (b) obtaining the size of the window required for the at least one series on the basis of the determination, and (c) utilizing the window having the predetermined size to determine data values to be stored in computer memory when calculating the formula when applied to other series of data values in the collection.

Abstract: An algorithm and handheld device adapted to select a subexpression of a mathematical expression. An expression string of the handheld device is selected, and the expression string is converted to a contiguous tokenized Polish representation (CTPR) of the expression, and the CTPR of the expression is loaded into an n-ary tree. The user may navigate the visual representation of the expression to select a subexpression. The handheld device is adapted to select the subexpression from the n-ary tree.

Abstract: A Finite Impulse Response (FIR) filter circuit (60) includes delay elements (63, 64, 66), multipliers (71, 72, 73, 74), a summing device (78), and a digital integrator (69) at the output of the FIR filter circuit (60). A method for processing data using the FIR filter circuit (60) includes differentially encoding data prior to storing or processing of the data. The method provides a technique for compressing data since less memory is needed to store derivative data. The method further includes integrating the derivative data using the digital integrator (69) to decompress the derivative data.

Abstract: A calculator comprises an input having an UNDO key for recovering cleared values. When displayed data or recorded data of memory is cleared by pressing one of deletion keys, the cleared data is pushed into a stack register. A flag register is set when the displayed data or recorded data is cleared by a deletion key. When the UNDO key is pressed and the flag register indicates that the displayed data or recorded data was cleared by the deletion key, a data entry is popped from the stack register, so as to recover the cleared value.

Abstract: Interpolating filter banks are constructed for use with signals which may be represented as a lattice of arbitrary dimension d. The filter banks include M channels, where M is greater than or equal to two. A given filter bank is built by first computing a set of shifts ?i as D?1 ti, i=1, 2, . . . M?1, where ti is a set of coset representatives taken from a unit cell of the input signal lattice, and D is a dilation matrix having a determinant equal to M. A polynomial interpolation algorithm is then applied to determine weights for a set of M?1 predict filters Pi having the shifts ?i. A corresponding set of update filters Ui are then selected as Ui=P*i/M, where P*i is the adjoint of the predict filter Pi. The resulting predict and update filters are arranged in a lifting structure such that each of the predict and update filters are associated with a pair of the M channels of the filter bank.

Abstract: A decimation system and decimation circuit for decimating waveform data on an oscilloscope. The decimation circuit is implemented using sixteen parallel 16-to-1 multiplexers connected in parallel to a data bus which selectively captures samples based on control signals generated by a sample counting circuit. Decimation factor and phase values can be input to program the amount of decimation performed by the circuit. The decimation system provides even more flexibility in controlling the decimation and is formed by combining several of the decimation circuits with corresponding analog-to-digital converters and memory segments.

Abstract: A novel Finite Impulse Response (“FIR”) filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (104). At least two slave sample and hold circuits (114, 118) connect to the master output. The slave sample and hold circuits (114, 118) operate at 1/k times the clock rate of the master sample and hold circuit (104), where k equals the number of slave sample and hold circuits (114, 118). A first multiplexer (126) multiplexes the slave outputs together. At least one tap block (129, 179, 207) is coupled to the first multiplexer (126) includes a multiplier (132, 180, 210), a summer (142, 142, 216), at least two slave sample and hold circuits (152, 154, 188, 190, 224, 226) and a second multiplexer (164, 200, 236). The slave sample and hold circuits (152, 154, 188, 190, 224, 226) run at 1/k times the clock speed of the master sample and hold circuit (126).

Abstract: A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Abstract: A higher-radix type divider is provided which is capable of obtaining a quotient at a high speed by performing a scaling on a divisor and by representing a partial remainder in a redundant binary notation. The divider for obtaining the quotient by referring to the divisor and dividend normalized respectively so as to satisfy a range of ½K or more and less an ½K+1 (k being a positive integer) and to a length of bits, out of all bits of the partial remainder, defined by a radix for operations and a maximum number of digits, is provided with a scaling factor generating section, a multiplying section, a divisor tripled-number generating section and a repetitive operating section.

Abstract: An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimated partial remainder W[j+1] for the next iteration, j+1, as 2*W[j]?Sj+1*D, where W[j] is the estimated partial remainder for the current iteration calculated during the prior iteration, Sj+1 is the quotient bit estimated for the next iteration, and D is the respective divisor bit. The estimated quotient bit for the next iteration is selected based on the calculated partial remainder. In the square-root mode, the first summing device calculates 2W[j]?2S[j]Sj+1, where W[j] is the estimated partial remainder and Sj+1 is the estimated result generated during the current iteration, j.