Patents Examined by Clifford Knoll
  • Patent number: 8793420
    Abstract: A system-on-chip (SoC), an electronic system including the same, and a method of operating the same are provided. The method includes setting real-time information indicating whether a master block is a real-time block in a real-time information register of the master block. A weight is set in a weight register of the master block. Buffer information of the master block is checked. A quality-of-service (QoS) signal is generated using the buffer information and the weight. A priority of the master block to use the bus is determined based on the QoS signal.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hong Ho Roh
  • Patent number: 8732366
    Abstract: In response to a reset condition, the state of a steady-state signal at an I/O pin of the serial communication port of an integrated circuit die is determined. The serial communication port is configured to support one of the plurality of serial communication protocols based upon the detected steady-state condition.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 20, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kevin R. Fugate, Edward W. Carstens, Jordan P. Legendre
  • Patent number: 8719482
    Abstract: A electronic device includes a bus, two electronic elements connected to the bus, and a controller. Each of the two electronic element is designated a logic unit number (LUN) and a first temporary buffer identified by the LUN for storing messages transmitted from or to the corresponding electronic element by the bus. The controller for obtaining the LUN of the message transmitted from/to the at least two electronic element, determining the temporary buffer which the message is stored according to the obtained LUN, storing the message to the determined temporary buffer, and transmitting the message stored in the temporary buffer to the corresponding electronic element or processing the message stored in the temporary buffer.
    Type: Grant
    Filed: April 28, 2012
    Date of Patent: May 6, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Chong Tu, Wei Shao
  • Patent number: 8713238
    Abstract: A communication circuit includes a communication port, a receiver an aligner, and a link recovery circuit. The communication port is configured to connect to a communication link and to disconnect from the communication link. The receiver is configured to generate, while the communication link is connected to the communication port, a serial sequence of received bits recovered from the communication link. The aligner is configured to decode a received sequence of blocks from the serial sequence of received bits. The blocks of the received sequence include data blocks and control blocks. The link recovery circuit is configured to reset the receiver in response to the blocks, in the received sequence after a first one of the control blocks and before a next one of the control blocks, numbering greater than a threshold number.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: April 29, 2014
    Assignee: Xilinx, Inc.
    Inventors: Killivalavan Kaliyamoorthy, Guru Prasanna Sethumadhavan
  • Patent number: 8706940
    Abstract: Multiprocessor systems often share access to a centralized memory and experience conflicting access requests. An arbitration unit mediates priorities of requestor preferably ensuring both priority and fairness. In this invention upon an access conflict the arbitrator grants access to one requestor having the highest priority level and stalls other conflicting requestors. If plural requestors have the same priority level, the arbiter grants access to one and stalls the others. The arbiter then adjusts the priority levels of the requestors. The priority of the requestor granted access is decreased by the number of stalled requestors. The stalled requestors have their priority levels increased by one. The arbitration decision is thus based on the stall history and the caused stall history of each requestor.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Timothy D. Anderson
  • Patent number: 8694706
    Abstract: The system and methods described herein may be used to implement NUMA-aware locks that employ lock cohorting. These lock cohorting techniques may reduce the rate of lock migration by relaxing the order in which the lock schedules the execution of critical code sections by various threads, allowing lock ownership to remain resident on a single NUMA node longer than under strict FIFO ordering, thus reducing coherence traffic and improving aggregate performance. A NUMA-aware cohort lock may include a global shared lock that is thread-oblivious, and multiple node-level locks that provide cohort detection. The lock may be constructed from non-NUMA-aware components (e.g., spin-locks or queue locks) that are modified to provide thread-obliviousness and/or cohort detection. Lock ownership may be passed from one thread that holds the lock to another thread executing on the same NUMA node without releasing the global shared lock.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: April 8, 2014
    Assignee: Oracle International Corporation
    Inventors: David Dice, Virendra J. Marathe, Nir N. Shavit
  • Patent number: 8683108
    Abstract: A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gerd K. Bayer, Beth A. Glendening, Thomas A. Gregg, Michael Jung, Elke G. Nass, Peter K. Szwed
  • Patent number: 8677046
    Abstract: A method for deadlock resolution in end-to-end credit protocol includes receiving a data frame and determining a number of credits required to transmit the data frame. The method also includes requesting and receiving credits from an end controller and responsively incrementing a credit counter. The method further includes determining if a value of the credit counter is greater than the number of credits required to transmit the data frame. Based on determining that the value of the credit counter is at least the number of credits required, the method includes transmitting the data frame to the end controller and decreasing the value of the credit counter by the number of credits required to transmit the data frame. Based on determining that the value of the credit counter is less than the number of credits required, the method includes transmitting a credit shortage notification to the end controller.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos I. Chrysos, Fredy D. Neeser, Kenneth M. Valk
  • Patent number: 8671304
    Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
  • Patent number: 8667196
    Abstract: A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 4, 2014
    Assignee: LSI Corporation
    Inventors: Srinivasa Rao Kothamasu, Debjit Roy Choudhury, Dharmesh Kishor Tirthdasani, Sajith Kizhakke Kalathil Achuthan Kutty, Jean Jacob
  • Patent number: 8667193
    Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: March 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Suren Mohan, Mark A. Landguth
  • Patent number: 8667205
    Abstract: A system for deadlock resolution in end-to-end credit protocol includes a plurality of source controllers configured to receive data frames on an incoming link, wherein each source controller includes a plurality of credit counters. The system also includes a plurality of end controllers configured to receive data frames from the plurality of source controllers, wherein each end controller includes a buffer credit counter, a plurality of request counters, and an output buffer. Each of the plurality of credit counters corresponds to one of the plurality of end controllers and stores a number of credits received from that end controller. The buffer credit counter of each end controller stores a number of available credits of the end controllers. Each of the request counters corresponds to one of the plurality of source controllers and stores a number of credit requests received from that source controller.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos I. Chrysos, Fredy D. Neeser, Kenneth M. Valk
  • Patent number: 8661176
    Abstract: The invention relates to a bidirectional wireless transmission system for serial format data signals between a “master” electronic device (3) and a “slave” energy meter (2) including a microcontroller (20) having a serial input port (RX). According to the invention, the serial format data signals are exchanged at short range via bidirectional electromagnetic coupling means (4) outputting a pulse on each rising or falling front in said serial format data signals. To transmit data signals from the “master” device (3) to the “slave” meter (2), the pulses at the output of the electromagnetic coupling means (4) are delivered to said serial input port (RX).
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: February 25, 2014
    Assignee: Itron France
    Inventor: Serge Bulteau
  • Patent number: 8661283
    Abstract: Apparatus, methods, and other embodiments associated with providing a correlation between a power distribution unit(s) and a device(s) are described. One example method includes storing first time series data that identifies, on a per power distribution unit (PDU) basis, current drawn from a set of PDUs. The example method may include storing second time series data that identifies, on a per device basis, power used by a set of related devices. With the two time series data available, the method may then provide a PDU-device correlation signal that identifies a correlation between current drawn from a PDU and power used by a device.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas E. Turicchi, Jr., Clifford A. McCarthy, Charles W. Cochran
  • Patent number: 8661171
    Abstract: Embodiments of the present invention provide a high throughput, low pin count, low power, and small area solution for the interface between a host device and a wireless communication circuit. In one embodiment of the invention, a system for wireless communication using a host-slave interface is disclosed. The system is comprised of a host device having a slave interface, and a wireless communication circuit having a master interface coupled to the host device's slave interface. The wireless communication circuit transfers data between a wireless network and the host device. Using such a system, a wireless communication system with a host-slave interface is produced.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: February 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shri Krishnan, Aman Singla, Manoj Unnikrishnan
  • Patent number: 8650327
    Abstract: A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shixiang Nie, Zhijun Chen, Zhihong Cheng
  • Patent number: 8635484
    Abstract: Systems, methods, and other embodiments associated with event based correlation of power events are described. One example method includes storing a power distribution unit (PDU) event data that identifies an occurrence of a suspected power event associated with a device. The method can then provide a PDU-server correlation signal that identifies a connection between a PDU and a device.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 21, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thomas E. Turicchi, Jr., Charles W Cochran, Darrel G. Gaston, Alan L. Goodrum
  • Patent number: 8631180
    Abstract: Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 14, 2014
    Assignee: Imagination Technologies, Ltd.
    Inventor: Jason Meredith
  • Patent number: 8626979
    Abstract: A signal transmission system includes a controller interface, a protocol engine to convert data based on at least one protocol, and a common protocol interface coupled between the controller interface and the protocol engine. The controller interface includes or is coupled to a common dispatcher, and the data is to be transmitted between the controller interface and protocol engine through the common protocol interface and common dispatcher. The same protocol engine may convert data into different protocols, with all of the converted data be transmitted to or received from the controller interface through the common dispatcher and common protocol interface.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventors: Jennifer C. Wang, Nai-Chih Chang, Beracoecha Alejandro Lenero, Yew-Kee E. Wong
  • Patent number: 8626978
    Abstract: To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: January 7, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Minoru Itakura