Abstract: Link startup systems, methods and devices associated with interconnects are described. Asymmetric lane connections are supported by, for example, independent renumbering of the connected lanes after an initial discovery process. Low-power, hibernating states of devices are supported by, for example, initialing alternating between transmission of startup and wakeup sequences over the interconnect between devices.

Abstract: Techniques and devices for transmitting data and information via a bus are provided. According to these techniques, data is transmitted in units or frames together with information that is required or useful for one or more of the transmission and the use of the data. If desired, at least some of the units or frames include a time slot within which freely selectable devices can output onto the bus data representing freely selectable information at freely selectable points in time.

Abstract: One embodiment relates to a clocking network interconnecting an array of transceivers. The clocking network includes first and second series of multiplexers, each multiplexer in the first and second series being adjacent to a transceiver. The first series of multiplexers selectively transmits clock signals in a first direction of the array, and the second series of multiplexers selectively transmits clock signals in a second direction of the array. Another embodiment relates to an integrated circuit with a programmable interface. The integrated circuit includes an array of physical media attachment circuits, phase-locked loop circuits, and a clock distribution network. The clock distribution network is arranged to be programmed into multiple segments. Each segment distributes a clock signal to a bounded range of the physical media attachment circuits in the array. Another embodiment relates to a method of distributing clock signals in an integrated circuit. Other embodiments and features are also disclosed.

Abstract: A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.

Abstract: The present invention relates to a transmitting node for transmitting data to a receiving node over at least one Ethernet link comprising a data communication unit arranged to transmit data over the at least one Ethernet link, and a control unit arranged to control the data communication unit so as to maintain the at least one Ethernet link in a link active state, characterized in that the control unit is arranged to operate in a first IDLE state in which IDLE data packets are transmitted periodically through the data communication unit over the at least one Ethernet link according to at least one predetermined IDLE data packet timing interval, and in said first IDLE state, power down at least one component comprised in the data communication unit in between the periodic transmissions of IDLE data packets. The present invention further relates to a method for use in a transmitting node, a receiving node, a network node and a system.

Abstract: A method and an apparatus for device dynamic addition processing, and a method and an apparatus for device dynamic removal processing. A dynamic addition dependency relationship list may be obtained from a BIOS, and dynamic addition processing is performed on a certain device to be dynamically added, according to the dynamic addition dependency relationship list; a user is prompted to dynamically add the target device, and when there is a certain device to be dynamically removed, a dynamic removal dependency relationship list and a dynamic addition dependency relationship list of a corresponding device may be obtained from the BIOS as needed, and dynamic removal analysis and processing are performed according to the combination of the dynamic removal dependency relationship list and dynamic addition dependency relationship list of the corresponding device, so as to prompt the user to dynamically remove the target device.

Abstract: A system including a first controller configured to communicate with a host via a first interface; a second controller configured to communicate with a storage device via a second interface, where the second interface is different than the first interface; and a bridge module configured to allow the second controller to transfer data between the storage device and the host and to allow the second controller to access memory of the host via the first interface during the transfer.

Abstract: Provided is a display apparatus including an image processing module and a display main body, wherein the image processing module includes: an image signal processor processing an image signal; a module terminal transmitting the processed image signal in a wired manner; and a module wireless communication unit transmitting wirelessly the processed image signal, and wherein the display main body includes: a main body terminal receiving the image signal from the module terminal which is detachably connected to the main body terminal; a main body wireless communication unit receiving the image signal from the module wireless communication unit; and a display unit displaying an image corresponding to the image signal; and a controller controlling the image signal to be transmitted selectively from the module terminal to the main body terminal or from the module wireless communication unit to the main body wireless communication unit.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.

Abstract: In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus.

Abstract: An asynchronous branching module (102) outputs transfer data received in accordance with a handshake protocol to any of branch destinations. An asynchronous arbitration module (101) merges transfer paths of the transfer data. A congestion detection module (111) receives an arbitration result signal from the asynchronous arbitration module (101) and outputs congestion information indicating presence/absence of congestion to a merge source. A congestion avoiding path calculation module (112) receives the congestion information and exclusively performs a process of storing the congestion information into a congestion information storage memory, and a process of making the asynchronous branching module (102) preferentially select, as a transfer branch destination, a branch destination generating no congestion information indicative of the presence of congestion from branch destinations leading to a destination, on the basis of the congestion information and the destination information of the transfer data.

Abstract: A transceiver apparatus includes a process, a first type of transceiver circuit for data transmission, a second type of transceiver circuit for data transmission, and a communications interface for communicating between the first type of transceiver circuit and an external device. The first type of transceiver circuit is co-located with a physical layer associated with the first type of transceiver circuit. In some embodiments, the first type of transceiver circuit can be, for example, a USB 2.0 transceiver circuit, and the second type of transceiver circuit can be a USB 3.0 transceiver circuit. The aforementioned external device can be an external USB device.

Abstract: A method for managing the operation of an information sensor for a meter, includes putting the sensor into a deep standby mode, in which a battery of the sensor does not supply electrical power in particular to a module for demodulating signals from the meter; connecting the sensor to the meter; detecting, using a detection module of the sensor, an information signal from the meter; removing the sensor from the deep standby mode in order to put same into an operative mode in which the battery supplies electrical power in particular to the demodulation module.

Abstract: Method, apparatus, and computer program product embodiments are disclosed to enable simplified configuring of a wireless docking group for wireless devices by allowing a wireless device to communicate its capabilities and characteristics of one or more wireless devices within a wireless docking group, using a new Wireless Docking Protocol, to a wireless docking station that will use that information and the Wireless Docking Protocol to define an optimal set of connections for wireless devices in the wireless docking group.

Abstract: Methods, apparatus, and product are disclosed for expanding functionality of hard drive bays in a computing system that include: providing, by a connector in a hard drive bay, access to two or more data communication busses of different type; receiving, by the connector of the hard drive bay, a device mounted within the hard drive bay; and communicately coupling, by the connector of the hard drive bay, the device to one of the data communication busses.

Abstract: The electronic device according to the present invention comprises a power supply; a processing section which has a nonvolatile register and performs predetermined processing by inputting and outputting data to and from the nonvolatile register on the basis of power fed from the power supply; an external signal inputting section for inputting an external signal to the processing section; and a power feed control section, which interrupts power feeding from the power supply to the processing section, while maintaining responsiveness to the external signal in a state in which the processing state of the processing section is stored in the nonvolatile register, and resumes power feeding from the power supply to the processing section in response to the external signal.

Abstract: A computer card comprising a first connector to enable the computer card to communicatively couple to an electronic device when the computer card is inserted into an externally accessible slot of the electronic device. The computer card further comprising an expansion slot configured to receive an expansion card therein. The computer card further comprising a second connector to facilitate coupling of a peripheral device to the computer card.

Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

Abstract: A timekeeping device that tracks the time provided by a digital broadcast and the protocol of that broadcast, defined by its data frame structure and modulation scheme, are adapted to allow for superior performance of the timekeeping devices in terms of range of operation, immunity to interference, ability to operate with lower cost antennas due to enhanced link robustness, and reduced energy consumption. The timekeeping device operates with infrequent receptions of the broadcast by relying on independent self-compensation. This alleviates the need for frequent receptions to ensure timing accuracy while reducing energy consumption. The mean and variability of successive measurements of timing drift are evaluated and an estimated upper bound for the drift-estimation error is set. Based on this bound, the device employs a reception strategy that relies on less frequent receptions, corresponding to the error in estimating the drift rather than to the magnitude of the drift itself.

Abstract: Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root (20) or endpoint (22) device. In conjunction with, for example, PCI Express specified I/O data buses (24), such devices provide for efficient transfer of serial data between systems and devices.