Abstract: The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics.

Abstract: Methods and systems for docking a laptop with Ethernet A/V bridging to guarantee services are disclosed and may include interfacing a portable computing device with a docking station using an Ethernet interface, and utilizing audio/video (AV) bridging for communicating data between the portable computing device and one or more devices coupled to the docking station. AV bridging may be utilized based on latency requirements of the data communication. The interfacing may include directly coupling an Ethernet port of the docking station to an Ethernet port of the portable computing device. Alternatively, the interfacing may include coupling an Ethernet port of the docking station to an Ethernet port of the portable computing device via an Ethernet cable. The portable computing device may be powered via the Ethernet interface, and may utilize power over Ethernet protocol. The docking station may include a passive or active docking station.

Abstract: An electronic system including modules connected in a ring network is provided. The modules communicate via ring interfaces. The ring interfaces are connected by inter-module links that include a control bus and combined address and data bus. The ring interfaces send and receive single-cycle transactions. The control bus signals the type of transaction and the source and destination modules. The ring interfaces forward transactions to their destinations and may send new transaction when a cycle is empty. Each read operation uses a read request transaction containing an address that is responded to with an acknowledgment transaction that includes the requested data. Each write operation uses two write requests, one containing an address and one containing data. The destination module signals completion of the write operation by sending an acknowledgment transaction.

Abstract: A system and method using messages to access registers and memory in a PCI Express communications link environment. Vendor defined PCI Express messages can be used to read and write to the memory-mapped or register space of a device. Four types of accesses are defined using this messaging approach, namely memory read, memory write, configuration read and configuration write. The type of register access desired is defined by the appropriate value in a vendor-specific type field in the header of the vendor defined message. If a PCI Express compliant device at the other end of the PCI Express link does not support these types of messages, the messages are silently discarded by the receiver and no error is reported.

Abstract: Various systems and methods for power management are disclosed herein. For example, a modular, adaptive power management system for use in a hard disk drive system is disclosed. This modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The host interface may be, for example, an ATA interface, a SATA interface, and/or other emerging serial interfaces such as MMC, CE-ATA or SDIO. The power manager system includes a power island register and an oscillation control register. Both the power island register and the oscillation control register are each at least indirectly writable via the firmware and via the host interface.

Abstract: Methods and apparatus are provided for virtualizing resources including peripheral components and peripheral interfaces. Peripheral component such as hardware accelerators and peripheral interfaces such as port adapters are offloaded from individual servers onto a resource virtualization switch. Multiple servers are connected to the resource virtualization switch over an I/O bus fabric such as PCI Express or PCI-AS. The resource virtualization switch allows efficient access, sharing, management, and allocation of resources.

Abstract: To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers.

Abstract: The present invention relates to improved methods for processing requests and sending data in a bus architecture. The present invention further relates to an improved bus architecture for processing requests and data. There is provided a method for processing read requests in a bus architecture comprising at least one master device connected to at least two slave devices via a bus. The architecture comprises an allocator for allocating incoming requests from the master device to a target slave device and an optimiser for each slave device. Each optimiser is for buffering incoming requests for the respective slave device. The method comprising the steps of: a) the master device sending a read request for a first slave device to the bus; b) the allocator generating a current-state indicator associated with the read request.

Abstract: A multicore processor provides for local power control at each of the cores which is used to lower the maximum operating frequency of cores by any amount above of the maximum operating frequency of the slowest core. This power savings is then used to increase the maximum operating frequency of the frequency balanced cores within a power constraint.

Abstract: An exemplary high speed data storage system includes hard disks, a first control panel, a second control panel and a midplane interconnected between each of the first and second control panels and the hard disks. Each of the first and second control panels includes a control chip and a connector. First and second printed circuit wires corresponding to the hard disks are layered on the first and second control panels for electrically connecting the control chip with the connector, respectively. The first printed circuit wires of the first control panel and the second printed circuit wires of the second control panel are arranged symmetrically with respect to each other, and an order of stacking circuit layers of the first printed circuit wires of the first control panel is the reverse of an order of stacking of circuit layers of the second printed circuit wires of the second control panel.

Abstract: Systems, methods and portable devices are provided for interconnecting one or more computing modules within an enclosure together to form an integrated system. A portable device may include a communication interface configured to be removably coupled to each computing module for interconnecting them together to form the integrated system. A portable device may also include memory configured to store an integrated system personality that serves as a point of authority for each computing module of the integrated system. The integrated system personality may include an identifier of the integrated system.

Abstract: An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller for controlling an operation of the interface under combined control of the clock line and the data line. The circuit has a plurality of further nodes for connecting to a plurality of further data lines. The controller has an operational mode for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.

Abstract: A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition, the system may be configured such that the initial wavefronts of these signals may travel in opposite directions along complementary signaling paths. For example, a timing reference signal that travels from a driving device (e.g., a memory controller) to several destination devices (e.g., memory devices) in a multi-drop/fly-by fashion may arrive at the destination devices in a given order. In contrast, associated information signals may travel from the driving device to the destination devices such that they arrive at the destination devices in the opposite order.

Abstract: Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.

Abstract: A switch apparatus includes first to third video graphics array (VGA) interfaces, first to sixth universal serial bus (USB) interfaces, a single-pole double-throw (SPDT) switch, and first to eighteenth electronic switches. The first VGA interface is connected to the second and third VGA interfaces through the electronic switches. The first USB interface is connected the second and third USB interfaces through the electronic switches. The fourth USB interface is connected to the fifth and sixth USB interfaces through the electronic switches. The SPDT switch is used to control the first VGA interface to be selectively connected to the second or third VGA interface, and control the first USB interface to be selectively connected to the second or third USB interface, and control the fourth USB interface to be selectively connected to the fifth or sixth USB interface.

Abstract: Systems and methods are provided that forward or route data streams using a plurality of processors, while maintaining the correct sequence of data packets within the data stream. Each interface may be associated with a respective one processor such that data packets received by an interface are handled by its respective one processor. Once a data packet is received by an interface, the processor associated with the interface may determine whether the received data packet is intended for another interface associated with another respective one processor. If the processor determines that the data packet is intended for another interface, the data packet may be forwarded to the processor associated with the other interface.

Abstract: A relay device includes: an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header; multiple virtual channels for storing data units, each of the multiple virtual channels storing a data unit in accordance with the destination information; a destination comparing section for determining the order of allocation of virtual channels at a relay device on the receiving end with respect to the data units that are stored on the multiple virtual channels by seeing if their destinations are the same; and an output section for outputting the stored data units preferentially through one of the virtual channels that has already allocated at the relay device on the receiving end.

Abstract: Systems and methods for transmitting and processing interrupts by embedding interrupt information into a serial data stream are disclosed. An event is detected and converted into an interrupt signal. The interrupt signal is converted into a special interrupt character or symbol sequence. The special interrupt character or symbol sequence is embedded into a serial data stream at the next available character or symbol boundary and transmitted to a receiving controller. The receiving controller strips the special interrupt character or symbol sequence from the serial data stream and raises a corresponding interrupt. The receiving controller processes the interrupt by interrupting normal processing to run an interrupt subroutine. Once the receiver has detected and raised an interrupt, it can return an acknowledgement character or symbol sequence by the same mechanism.

Abstract: Certain aspects of a method and system for a hardware-based implementation of USB 1.1 over a high-speed link may comprise translating at a client side of a client server communication system, USB protocol messages comprising a first USB standard to corresponding encapsulated USB protocol messages, wherein the USB protocol messages comprising the first USB standard are received from a client device at the client side of the client server communication system. The translated corresponding encapsulated USB protocol messages may be communicated from the client side to a server at a server side of the client server communication system.

Abstract: An indicator control apparatus includes a bus connector, a signal converting unit, an address configuring unit, and an indicating unit. The signal converting unit receives bus signals from the bus connector. The address configuring unit sets an address of the signal converting unit. The signal converting unit converts the bus signals to digital input/output (I/O) signals in response to the address of the signal converting unit matching with the bus signals. The indicating unit is driven by the I/O signals and correspondingly displays information.