Abstract: A low dielectric constant film having silicon-carbon bonds and dielectric constant of about 3.0 or less, preferably about 2.5 or less, is provided. The low dielectric constant film is deposited by reacting a cyclic organosilicon compound and an aliphatic organosilicon compound with an oxidizing gas while applying RF power. The carbon content of the deposited film is between about 10 and about 30 atomic percent excluding hydrogen atoms, and is preferably between about 10 and about 20 atomic percent excluding hydrogen atoms.

Abstract: In one embodiment, a method comprises placing a first and a second substrate into a reaction chamber, the first substrate being made of an indium antimonide material and having a first surface and the second substrate being made of a silicon or a silicon dioxide material and having a second surface; exposing the first and second surfaces to an oxygen plasma; forming a bond between the first and the second substrates by placing the first surface in contact with the second surface; and annealing the first and the second substrates to strengthen the bond.

Abstract: The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

Abstract: The present invention provides a semiconductor device formed with a diode array together with bipolar transistors, which is capable of preventing the occurrence of crystal defects developed in cross patterns in deep trench regions and improving device yields, and a method of manufacturing the semiconductor device. A semiconductor device includes a LOCOS oxide film which isolates a plurality of diodes in an X direction, and deep trenches which isolate the plurality of diodes in a Y direction. The depth of each of the deep trenches is deeper than a high density layer embedded below a collector layer of each bipolar transistor. A shallow trench may be used as an alternative to the LOCOS oxide film.

Abstract: An electronic device containing a polythiophene wherein R represents a side chain, m represents the number of R substituents; A is a divalent linkage; x, y and z represent, respectively, the number of Rm substituted thienylenes, unsubstituted thienylenes, and divalent linkages A, respectively, in the monomer segment subject to z being 0 or 1, and n represents the number of repeating monomer segments in the polymer or the degree of polymerization.

Abstract: An integrated circuit chip 903, which has a plurality of pads 903b and non-reflowable contact members 1201 to be connected by reflow attachment to external parts. Each of these contact members 1201 has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface 1202 on each end and a layer of reflowable material on each end. Each member is solder-attached (1204) at one end to a chip contact pad 903b, while the other end (1203) of each member is operable for reflow attachment to external parts.

Abstract: A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.

Abstract: This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A strained silicon layer fabrication employs a substrate having successively formed thereover: (1) a first silicon-germanium alloy material layer; (2) a first silicon layer; (3) a second silicon-germanium alloy material layer; and (4) a second silicon layer. Within the fabrication each of the first silicon-germanium alloy layer and the second silicon-germanium alloy layer is formed of a thickness less than a threshold thickness for dislocation defect formation, such as to provide attenuated dislocation defect formation within the strained silicon layer fabrication.

Abstract: After forming domain inverted layers 3 in an LiTaO3 substrate 1, an optical waveguide is formed. By performing low-temperature annealing for the optical wavelength conversion element thus formed, a stable proton exchange layer 8 is formed, where an increase in refractive index generated during high-temperature annealing is lowered, thereby providing a stable optical wavelength conversion element. Thus, the phase-matched wavelength becomes constant, and variation in harmonic wave output is eliminated. Consequently, with respect to an optical wavelength conversion element utilizing a non-linear optical effect, a highly reliable element is provided.

Abstract: A field effect transistor in which a continuous semiconductor layer comprises: a) an organic semiconductor; and, b) an organic binder which has an inherent conductivity of less than 10?6Scm?1 and a permittivity at 1,000 Hz of less than 3.3 and a process for its production comprising: coating a substrate with a liquid layer which comprises the organic semiconductor and a material capable of reacting to form the binder; and, converting the liquid layer to a solid layer comprising the semiconductor and the binder by reacting the material to form the binder.

Abstract: A method is provided for forming an amorphous carbon layer, deposited on a dielectric material such as oxide, nitride, silicon carbide, carbon doped oxide, etc., or a metal layer such as tungsten, aluminum or poly-silicon. The method includes the use of chamber seasoning, variable thickness of seasoning film, wider spacing, variable process gas flows, post-deposition purge with inert gas, and post-deposition plasma purge, among others, to make the deposition of an amorphous carbon film at low deposition temperatures possible without any defects or particle contamination.

Abstract: A method of synthesizing an aminosilane source reagent composition, by reacting an aminosilane precursor compound with an amine source reagent compound in a solvent medium comprising at least one activating solvent component, to yield an aminosilane source reagent composition having less than 1000 ppm halogen.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes by exposing the plurality of conductive regions formed in the semiconductor substrate, wherein an impurity concentration of the conductive regions is reduced due to the process for forming the contact holes; filling a metal material in the contact holes and forming a plurality of contact plugs; sequentially forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the contact plugs; forming a plurality of metal line patterns, wherein the metal line patterns pass through the third interlayer insulation film, the second etch barrier film a

Abstract: A method of fabricating a memory card. The method comprises the initial step of providing a leadframe which has a dambar and a plurality of contacts, each of the contacts being attached to the dambar by at least one tie bar. A layer of tape is applied to the leadframe such that the tape covers at least portions of the top contact surfaces of the contacts, at least portions of the top tie bar surfaces of the tie bars, and at least a portion of the top dambar surface of the dambar. Thereafter, the tie bars are removed from the leadframe. At least one semiconductor die is then electrically connected to the leadframe, with a body thereafter being formed on the leadframe such that the semiconductor die and the tape are covered by the body and the bottom contact surfaces are exposed in an exterior surface thereof.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: The present invention discloses a method for forming an element isolation film of a semiconductor device, comprising the steps of: sequentially forming a pad oxide film, a pad nitride film and a mask oxide film on a semiconductor substrate on which a first region for forming a high voltage device and a second region for forming a low voltage device or a flash memory cell are defined; etching the mask oxide film, the pad nitride film and the pad oxide film in the first region and the mask oxide film in the second region, and forming an oxide film for the high voltage device in the first region; removing the residual pad nitride film in the second region; removing the nitride film and partially removing the oxide film for the high voltage device in the first region, wherein the oxide film for the high voltage device has a third thickness; removing the residual pad oxide film in the second region; partially removing the oxide film for the high voltage device in the first region according to a cleaning process, w

Abstract: Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.