Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.

Abstract: A field-effect transistor (FET) based synchronous rectifier for emulating a diode, comprising: a first terminal (20) and a second terminal (30); a first FET (M1) and a second FET (M2), wherein the second FET (M2) is adapted to control operation of the first FET (M1) to thereby allow unidirectional current flow when the two terminals (20, 30) are connected with an external circuit; and wherein the FET based synchronous rectifier comprises a fully integrated single-chip device (10) adapted to emulate a diode.

Abstract: The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET. A primary conductive structure connecting the first FET and the second FET in series provides a primary parasitic inductor within the power path. A first secondary conductive structure connected to both a gate and a source of the first FET provides a first secondary parasitic inductor within a first gate path, and a second secondary conductive structure connected to both a gate and a source of the second FET provides a second secondary parasitic inductor within a second gate path. The first secondary conductive structure and the second secondary conductive structure are configured such that mutual coupling between the first secondary parasitic inductor and the primary parasitic inductor and mutual coupling between the second secondary parasitic inductor and the primary parasitic inductor are substantially symmetrical.

Abstract: A system for distributing DC bus voltage and control power to multiple motors includes a rectifier front end supplying a DC bus voltage and a DC control voltage. Both the DC bus voltage and the DC control voltage are distributed via a common set of conductors. Diodes are operatively connected between the DC control voltage and the common set of conductors. The diodes allow forward conduction of the DC control voltage and distribution of control power to distributed devices when the DC bus voltage is not present. Once the DC bus voltage is present, the diodes block conduction of the DC control voltage. Each of the distributed devices are configured with an internal power supply that is operative to generate an internal control voltage from either the DC control voltage or the DC bus voltage.

Abstract: An electronic component is switched under the control of a pulse-width modulation signal. The electronic component outputs an output signal that is controlled by a control signal. The switching on or off is initiated within a pulse-width modulation cycle period at a level change time by a change of the pulse-width modulation signal. The control signal is set within each PWM cycle period to a first control value between the level change time and a first switching time, to a second control value between the first switching time and a second switching time, and to a third control value from the second switching time until a final gate-voltage value is reached on the gate of the electronic component. Each switching time of a PWM period is determined in dependence on an amplitude value determined during a preceding PWM cycle period, to limit amplitudes of the oscillation of the output signal.

Abstract: In a gate drive circuit of which an N-channel MOSFET and a P-channel MOSFET are connected in a push-pull manner to amplify an input pulse signal and drive an output element, a temperature correction circuit is connected between gate terminals of the N-channel MOSFET and the P-channel MOSFET. The temperature correction circuit lowers each of gate voltages of the N-channel MOSFET and the P-channel MOSFET as ambient temperature rises.

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.

Abstract: A capacitor-insulated semiconductor relay includes an RC oscillation circuit, a waveform regulation circuit, a booster circuit, a charging/discharging circuit, and an output circuit. The RC oscillation circuit generates first and second signals that are inverse in phase to each other. The waveform regulation circuit increases rise and fall times of the first signal, and rise and fall times of the second signal. Output signals from the waveform regulation circuit are respectively inputted to first and second high dielectric strength capacitors and that are provided in the booster circuit and connected in parallel to each other. The booster circuit receives the output signals from the waveform regulation circuit to generate a predetermined voltage. The output circuit is driven based on the predetermined voltage.

Abstract: A semiconductor device includes a main bi-directional switch formed on a semiconductor substrate and having first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain. The semiconductor device further includes a discharge circuit having a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch and connected in a common source configuration to the semiconductor substrate. The plurality of individual transistors or the auxiliary bi-directional switch includes a first drain connected to the first source of the main bi-directional switch, a second drain connected to the second source of the main bi-directional switch, and first and second gates each decoupled from gate drive circuitry so that the first and the second gates are controlled at least passively and based on a state of the main bi-directional switch.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: A drive circuit for a power switching transistor includes a first pull-up drive transistor connected in parallel with a second pull-up drive transistor, a first pull-down drive transistor coupled to the first and second pull-up drive transistors in series to drive the power switching transistor. When control signal is at a high level, the first pull-up driver is turned on, and the first pull-down driver is turned off. The second pull-up drive transistor being in turn-on or turn-off state is determined by comparing voltage of the power supply with the threshold value. When voltage of the power supply is lower than the threshold value, the first and second pull-up drive transistor are driven together. When voltage of the power supply is higher than the threshold value, the second pull-up driving transistor is turned on only after the driving output is slightly larger than the Miller plateau voltage.

Abstract: A gate of the first p-type MOS transistor and the first and second control circuits are electrically coupled to a first node. The first control circuit lowers a voltage or the first node between a first time and a second time at which the first p-type MOS transistor is off. The second control circuit lowers the voltage of the first node between a third time and a fourth time at which the first p-type MOS transistor is on. The second time is later than the first time. The fourth time is later than the second and third times. The first p-type MOS transistor is turned on during a first period. A voltage decrease amount of the first node per unit time in the first control circuit is greater than that in the second control circuit.

Abstract: A capacitor-insulated semiconductor relay includes an RC oscillation circuit, a waveform regulation circuit, a booster circuit, a charging/discharging circuit, and an output circuit. The RC oscillation circuit generates first and second signals that are inverse in phase to each other. The waveform regulation circuit increases rise and fall times of the first signal, and rise and fall times of the second signal. Output signals from the waveform regulation circuit are respectively inputted to first and second high dielectric strength capacitors and that are provided in the booster circuit and connected in parallel to each other. The booster circuit receives the output signals from the waveform regulation circuit to generate a predetermined voltage. The output circuit is driven based on the predetermined voltage.

Abstract: A system to power pressure pumps and auxiliary equipment for oil and gas operations. The system includes a mobile system controller and energy storage unit electrically connected to pressure pumping and auxiliary loads. The system can also include a power generation source. One application of the technology is to pump fluids to an oil and gas end user which can be an oil or gas well, pipeline or plant. The system can be modularized and can be fully mobile and transportable by a variety of means.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.

Abstract: A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Abstract: The invention relates to a mixer for generating an analog output signal XOUT from an analog input signal XIN using a mixing signal having a mixing frequency fMIX, the mixer comprising: a scaler being configured to sample the analog input signal XIN at a plurality of discrete points in time k with a sampling frequency fS to obtain a sampled analog input signal XIN[k] having a continuous signal value, and to generate the analog output signal XOUT having a continuous signal value by scaling the sampled analog input signal XIN[k] on the basis of a plurality of scaling coefficients A[k], wherein the scaling coefficients A[k] are a time-discrete representation of the mixing signal.

Abstract: An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

Abstract: A disclosed circuit arrangement detects the supply voltage level to the “device” (SoC, chip, SiP, etc.) and adjusts bias voltages to receiver and transmitter circuits of the device to levels suitable for the device in response to the supply voltage ramping-up during a power-on reset (“POR”) sequence. The circuitry holds the receiver output at a constant logic value while the supply voltage is ramping up and the POR signal is asserted. The disclosed circuitry also protects the transceiver as the voltage domain of the input signal is unknown and the voltage between any two terminals of a transistor of the transceiver cannot exceed a certain level.