Abstract: A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. Each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment provides a plurality of allow mode signals to the other control segment.

Abstract: A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. However, each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment comprises a plurality of synchronous countdown register timers.

Abstract: A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.

Abstract: A cache including a tag storage which compares a portion of the tag address (a "mini-tag") to a respective portion of a request address is provided. If the mini-tag matches, then the way associated with the tag having a match is the way selected for conveying data bytes to the output of the cache. The mini-tag comparison is performed on a field of address bits different from the index field, and the comparison is performed in parallel with the index field decode. The way selection is qualified with the index field decode such that one set and one way of the set is selected for conveying bytes from the cache. The access time of the present cache structure is substantially similar to a direct-mapped cache. However, the present cache strucuture is a set-associative structure. The hit rate and thrashing insensitivity of a set-associative cache are maintained by the present cache.

Abstract: A CD-ROM disk drive receives commands from a host computer. In order to speed up the data accessing response time of the CD-ROM, a method is provided for rearranging the order in which the commands received from the host computer access data contained in sequentially enumerated blocks on the CD-ROM in the disk drive. According to the disclosed method, three queues are set up for holding the logical block addresses of blocks which are to be accessed by the received commands. An execution queue stores addresses of disk blocks to be accessed by a currently executed command. A wait queue stores addresses of disk blocks to be accessed by the next command after the commands accessing addresses of disk blocks stored in the execution queue. A free queue stores addresses of disk blocks to be accessed by the continuously transmitted commands.

Abstract: A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Abstract: A user interacts with a computer system having a display unit, a processor, a memory and a Cartesian selection device by activating a first major feature; displaying a plurality of labels representing a plurality of options for said first major feature; selecting one of the options by manipulating the Cartesian selection device in a first axis; displaying a plurality of suboptions for the selected option; selecting one of the suboptions by manipulating the Cartesian selection device in a second axis; and selecting a second major feature by either selecting an indicia of the second major feature displayed on the display unit or using a hardbutton coupled to the processor. Both the first and second major feature comprising one of faxing, scanning, and voice mail functions. The user interface system for the computer system comprises a grid of possible user functions. The grid is made up of a plurality of rows and a plurality of columns.

Abstract: A disk drive has two channels of upper interfaces, and one channel is connected to a disk array controller, and the other channel is connected between a plurality of disk drives. A data disk drive reads the old data on the recording medium, calculates the exclusive OR of the old data and the corresponding data from the disk array controller, and transfers it to a parity disk as pseudo-parity data from the other channel. The parity disk drive reads the old parity data on the recording medium, calculates the exclusive OR of the old parity data and the pseudo-parity data, and writes it as new parity data.

Abstract: A method and system for altering data contained in a structure without requiring a lock to the structure itself. The method and apparatus retrieve a pointer to the structure from a location responsible for maintaining a pointer to the structure. The structure has a reference count for indicating processes that are currently using the data residing within the structure itself. The reference count is then atomically incremented and a new structure is obtained. The data contained in the structure, to be altered, is then copied to the new structure. The new structure also has a reference count for indicating processes that are currently using the data residing in the new structure. The reference count of the new structure is then set to indicate that a single process is accessing the new structure. Thereafter, the pointer in the responsible location for the structure, to be altered, is atomically replaced with a pointer to the new structure.

Abstract: A method and apparatus for automatically synchronizing the polarity of video signals generated by a graphics controller card to a display monitor is described. The present invention includes hardware circuitry comprising a storage unit, a detection unit, a selection unit that store, detect, and select input video signals, particularly a vertical and a horizontal synchronization signals, with the same or different polarity that are received from the graphics controller to a display monitor. The present invention synchronizes the polarity of input vertical and horizontal synchronization signals from the graphics controller prior to transmitting the sync signals to the display monitor. The detect and selection circuits of the present invention enable polarity of input sync signals to be synchronized without the use of software as practiced in the prior art.

Abstract: In a data storage system using a flash memory unit and an HDD, the storage area of the flash memory unit is logically divided into a permanent storage area, a non-volatile cache area, which are used as cache memory areas of the HDD, and a high-speed access area. These divided areas are individually managed. The permanent storage area stores data which is used frequently for a relatively long time period. The non-volatile cache area is used as an ordinary cache memory area in which data, which is updated relatively frequently, is stored. The high-speed access area is a storage area to be used by, e.g. an operating system (OS) of a host system. For example, a swap file, which needs to be accessed at high speed, is shifted into the high-speed access area.

Abstract: A bit map is maintained by a provider object of a name server to keep track of names cached by a cache object of the client. The bit map is indexed by performing a hash of the name. When a name is looked up by the server on behalf of a client, the server hashes the name, and sets the bit in the bit map indexed by the result of the hash modulo the size of the bit map. The result of the hash is returned to the client and is stored with the entry in the cache. A bit "set" in the bit map indicates that the client caches at least one name that hashes into the bit. When the server invalidates a name, a hash of the name to be invalidated is used to find the corresponding bit in the bit mask. If the bit is set, the server sends an invalidation request to the client. The invalidation request includes the result of the hash, and the size of the provider's bit map. The client invalidates all entries that hash into the specified bit in the bitmap on the server.

Abstract: A backup unit comprises a first storage means containing at least one program and a setup file in which the operating environment of that program is written; a second storage means used when the first storage means has a fault; a duplication means for duplicating the program and the setup file contained in the first storage means, into the second storage means; and an identifier conversion means for converting identifiers included in the setup file of the first storage means and relating to the first storage means, into identifiers relating to the second storage means, when the duplication is performed. Therefore, when the operation of an information processor is stopped due to a fault in the first storage means, the second storage means enables temporary operation of the information processor. In addition, it is possible to employ, as the second storage means, a recording medium that is lower in price and writing speed than the first storage means.

Abstract: Methods and associated apparatus in a RAID storage subsystem to enhance the performance of write operations for sequences of large buffers generally non-aligned with stripe boundaries in the RAID storage subsystem. In particular, the methods identify a starting non-aligned portion of each large buffer to be written to the RAID storage subsystem, an ending non-aligned portion of each large buffer to be written to the RAID subsystem, and a larger middle portion of the large buffer to be written to the RAID subsystem which is aligned with stripe boundaries of the RAID storage subsystem. The stripe-aligned middle portion is written to the RAID storage devices in a cache write through mode using stripe write operations to maximize data throughput. The starting and ending portions identified by the methods of the present invention are written to the cache memory in a write back mode such that they will eventually be posted to the RAID storage devices in due course through normal RAID processing.

Abstract: A L2 (high-level) cache according to the present invention implements an efficient pipelined algorithm for flushing the high-level cache and back-invalidating a L1 (low-level) cache. Initially, an address calculation stage calculates the address of a directory entry contained in an array of directory entries every clock cycle. Connected to this address calculation stage is a directory entry lookup stage. The directory entry lookup stage receives an address from the address calculation stage and retrieves the directory entry to be modified from the array of directory entries. Finally, a directory entry modification stage, connected to the directory entry lookup stage, receives the directory entry from the directory entry lookup stage. The directory entry modification stage first looks to see if the directory entry is not marked as invalid. If the directory entry is already marked as invalid, no further processing need be performed on the directory entry.

Abstract: A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.

Abstract: A database management system incorporating an intermediate level of storage medium. Software of the DBMS controls the transfer of data between a primary, secondary and intermediate storage mediums. This transfer is under control of the DBMS and is not transparent to the DBMS. The intermediate storage medium has an access time that is shorter than the access time of the secondary storage medium. During operation of the DBMS, data is read from the secondary storage medium and held in the primary storage medium until the storage medium is full. Thereafter, as additional data is read by the DBMS from the database stored on the secondary storage medium, data is transferred to the intermediate storage medium under control of the DBMS, thus preserving the benefit of having the data read into the primary storage medium.

Abstract: A disk array server has a cache and a log drive wherein data blocks, as received are written synchronously to both the cache and the log drive, the cache being written back to the disk array as opportunity affords. The log drive is managed so, when full, data is overwritten in the order first stored on the log drive. Data blocks written to the log drive are flagged as to whether the same block in cache has been written to the disk array, and the flags are updated as the cache is written back to the disk array. In the event of a power failure, data lost from the volatile cache as not yet written to the disk array may be recovered from the log drive. In one embodiment, the recovery is automatic on startup after a power failure.

Abstract: The present invention relates to a method for reducing overheads of cache coherence enforcement in a shared-bus multiprocessors apparatus by utilizing a self-invalidation technique at local processor nodes as an extension to write-invalidate protocols in the shared-bus environment, and to an apparatus therefor.

Abstract: A circuit for internally caching a memory device having a main memory is comprised of a cache memory of smaller size than the main memory for storing certain of the same data stored in the main memory. A tag memory is provided for mapping the information stored in the cache memory. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom. The cache memory, tag memory, and logic circuit are carried internally in the memory device.