Patents Examined by Connie C. Yoha
  • Patent number: 11127436
    Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jiyun Li
  • Patent number: 11120857
    Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 14, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Akhilesh Jaiswal, Bipul C. Paul
  • Patent number: 11120863
    Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 14, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Farrukh Aquil, Vaishnav Srinivas, Mahalingam Nagarajan, Yong Xu
  • Patent number: 11120875
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 14, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Gou Fukano
  • Patent number: 11107511
    Abstract: A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 31, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jongsun Park, Woong Choi, Geon Ko
  • Patent number: 11081166
    Abstract: Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Werhane, Jason M. Johnson, Yoshinori Fujiwara, Tyrel Z. Jensen, Daniel S. Miller, David E. Jefferson, Vivek Kotti
  • Patent number: 11074946
    Abstract: A voltage differential sense amplifier circuit for a semiconductor memory circuit is disclosed. The voltage differential sense amplifier circuit includes a first and second pluralities of transistors. A first bias control circuit is included to bias the first plurality of transistors. The first bias control circuit is connected to body terminals of the first plurality of transistors for providing a temperature dependent first bias voltage to control threshold voltages of the first plurality of transistors. The temperature defendant first bias voltage is generated based on junction leakages at the body terminals of the first plurality of transistors. A second bias control circuit is included to bias the second plurality of transistors. The second bias control circuit is connected to body terminals of the second plurality of transistors for providing a temperature dependent second bias voltage to control threshold voltages of the second plurality of transistors.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 27, 2021
    Assignee: NXP B.V.
    Inventors: Jainendra Singh, Jwalant Kumar Mishra, Patrick van de Steeg
  • Patent number: 11049557
    Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yun-Chen Chou, Yung-Feng Lin, Hsin-Yi Ho
  • Patent number: 11049566
    Abstract: A request to perform a write operation at a memory component can be received. A destination block of the memory component to store data of the write operation can be determined. A voltage pulse can be applied to the destination block that places a memory cell of the destination block at a voltage level associated with a high voltage state. Responsive to applying the voltage pulse to the destination block, an erase operation for the destination block can be performed to change the voltage level of the memory cell from the high voltage state to a low voltage state. A write operation can be performed to write the data to the destination block that is at the low voltage state.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 29, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe
  • Patent number: 11037639
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a read operation controller configured to provide a read command to a memory device and receive read data corresponding to the read command, a read fail determiner configured to determine, based on the read data, whether a read operation has passed or failed, and to generate read information including a result of the read operation and information about performance of the read operation and a read fail processor configured to select, based on the read information, one of a read retry operation, among a plurality of read retry operations, to be performed on the selected page and an operation of setting a control time for a bit line coupled to the selected page, and to control the memory device to perform the selected operation.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Ho Her, Dong Hyun Kim, Seung Il Kim, Youn Ho Jung
  • Patent number: 11031087
    Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 11017831
    Abstract: Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 11017845
    Abstract: A method includes generating a voltage difference indication between a previous voltage on the bit line of a DRAM and a current voltage on a bit line. In an embodiment, the previous voltage corresponds to a logic 1 voltage or a logic 0 voltage stored in a previous DRAM cell of a column of DRAM cells, the current voltage corresponds to a logic 1 voltage or a logic 0 voltage being stored in the current DRAM cell of the column of DRAM cells, and the bit line is coupled to the column of DRAM cells. When the current DRAM cell is in a read mode, the method further includes the following steps: Generating a read voltage reference based on the voltage difference indication; Generating a read output voltage based on the read voltage reference; Supplying the read output voltage on to the bit line; and Outputting a representation of the read output voltage.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 25, 2021
    Assignee: SigmaSense, LLC.
    Inventors: Daniel Keith Van Ostrand, Gerald Dale Morrison, Richard Stuart Seger, Jr., Timothy W. Markison
  • Patent number: 11011222
    Abstract: Various implementations described herein refer to an integrated circuit having an array of bitcells coupled between at least one pair of bitlines including a first bitline and a second bitline that is a complement of the first bitline. The integrated circuit may include at least one pair of ancillary lines disposed adjacent to the at least one pair of bitlines, and the at least one pair of ancillary lines include a first ancillary line disposed adjacent to the first bitline and a second ancillary line disposed adjacent to the second bitline. The integrated circuit may include multiple pairs of passgates coupled between the at least one pair of bitlines and the at least one pair of ancillary lines.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 18, 2021
    Assignee: Arm Limited
    Inventors: Marlin Wayne Frederick, Jr., Ronald Paxton Preston, Andy Wangkun Chen, Yew Keong Chong
  • Patent number: 10992223
    Abstract: A semiconductor device capable of stabilizing an internal voltage is provided. According to one embodiment, the semiconductor device comprises a stabilized power supply circuit for generating a first voltage, a charge pump circuit for generating a second voltage different from the first voltage using the first voltage, the COUT2 including a comparison circuit for comparing the second voltage with a reference voltage, and a dummy load circuit controlled to be turned on or off in response to a comparison result signal COUT2 outputted from the comparison circuit, and the Dummy load circuit receives the comparison result signal COUT2 and is turned on for a predetermined period, whereby at least a part of a current IDD based on the first voltage flows into the dummy load circuit.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hidetoshi Ozoe
  • Patent number: 10984846
    Abstract: A sense amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node in which the reference path is coupled to a cell reference circuit during a read, wherein the first current load device includes a control input for controlling a current of the reference path. The cell path includes a second current load device and a cell comparison node in which the cell path is coupled to a memory cell during a read, wherein the second current load device includes a control input for controlling a current of the cell path. The comparator circuit indicates a data value being stored in the memory cell based on a comparison of voltages at the reference and cell comparison nodes. Different signals are provided to the control inputs of the first and second current load devices.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 20, 2021
    Assignee: NXP USA, Inc.
    Inventors: Karthik Ramanan, Jon Scott Choy, Jacob Williams
  • Patent number: 10964720
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Patent number: 10964362
    Abstract: Disclosed is a three-port static random access memory (3P-SRAM) that performs XNOR operations. The cell has a write port and first and second read ports. Read operations are enabled through either the first read port using a first read wordline and a common read bitline or the second read port using a second read wordline and the common read bitline. Read wordline activation is controlled such that only one read wordline is activated (i.e., receives a read pulse) at a time. As a result, a read operation through either read port effectively accomplishes an XNOR operation. Also disclosed is a memory array, which incorporates such cells and which performs XNOR-bitcount-compare functions. Since XNOR-bitcount-compare functions are used in XNOR-NET type binary neural networks (BNNs), the memory array can be employed for implementing such a BNN designed for improved performance, scalability, and manufacturability. Also disclosed is an in-memory computing method.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 30, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Zhewei Jiang, Muhammed Ahosan UL Karim, Xi Cao, Vivek Joshi, Jack M. Higman
  • Patent number: 10950290
    Abstract: A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 16, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Chang Lu, Wen-Jer Tsai
  • Patent number: 10937466
    Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-hwan Jeon