Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

Abstract: An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.

Abstract: An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

Abstract: A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell, and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Abstract: Apparatuses for providing pads included in external terminals of a semiconductor device are described. An example apparatus includes a memory cell array, a data queue (DQ) circuit, a data pad and a power pad. The memory cell array may include one or more memory cells. In a write operation, the data pad receives write data and provides the write data to the DQ circuit. The DQ circuit receives the write data and provides the write data to the memory cell array. In a read operation, the DQ circuit receives read data from the memory cell array and provides the read data. The data pad receives the read data from the DQ circuit and provides the read data. The power pad provides a power supply voltage. The data pad and the power pad are disposed across from each other with respect to the DQ circuit.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Abstract: This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row.

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

Abstract: An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets.

Abstract: The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode.

Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for providing refresh logic, such as row hammer refresh circuitry, in a location on a memory die apart from a bank logic region of the memory die. In some examples, at least some of the components of the row hammer refresh circuitry may be shared between banks of the memory.

Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.