Abstract: According to one embodiment, a screening method includes performing a first screening operation on a memory device at a first temperature to detect a defect in magnetoresistive effect elements of the memory device, replacing a first magnetoresistive effect element that is determined as defective in the first screening operation by substituting a second magnetoresistive effect element disposed in a redundancy area of the memory device for the first magnetoresistive, and performing a second screening operation on the memory device at a second temperature higher than the first temperature if the first screening operation detects a defect. Each of the first screening operation and the second screening operation includes writing data into the magnetoresistive effect element, reading data from the magnetoresistive effect element after the writing, and determining a magnetoresistive effect element is defective when the data as written does not match the data as read.

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

Abstract: A reference voltage generation circuit may be provided. The reference voltage generation circuit may be configured to generate a reference voltage according to a voltage set code. The reference voltage generation circuit may include a voltage level stabilizer. The reference voltage generation circuit may be configured to deactivate the voltage level stabilizer when a level of the reference voltage changes based on the voltage set code.

Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Abstract: To provide a search device with less memory consumption, the search device includes a first associative memory searched with a first search key, a second associative memory searched with a second search key, a concatenated search data generating unit that generates first search information based on hit information including multiple hits in the first associative memory, and a search key generating unit that includes a first key generating unit generating a portion of search data as the first search key and a second search key generating unit generating the first search information and another portion of the search data as the second search key.

Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: A logic circuit may include at least one magnetic tunnel junction device including a first layer configured to receive a particular input signal and a second layer connected to a node, and an inverter connected to the node and configured to generate an output signal by inverting a signal of the node, wherein the inverter includes a transistor on a substrate, and the at least one magnetic tunnel junction device is on an upper portion of the transistor. The at least one magnetic tunnel junction device may include first and second magnetic tunnel junction devices configured to receive first and second input signals, respectively. The logic circuit may include a magnetic tunnel junction device and a reference resistor configured to receive a second input signal, the reference resistor connected to the node, the reference resistor having a reference resistance. The logic circuit may be included in an apparatus.

Abstract: An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Abstract: A control device for writing data into a flash memory unit includes a determining circuit and a writing circuit. The determining circuit is arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time. The writing circuit is arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only. The determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time. The writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only.

Abstract: The memory cell includes a read selection transistor, a program selection transistor, and an anti-fuse capacitor. The read selection transistor has a first terminal coupled to a bit line, a second terminal, and a control terminal coupled to a read word line. The program selection transistor has a first terminal coupled to the second terminal of the read selection transistor, a second terminal coupled to a high voltage control line, and a control terminal coupled to a program word line. The anti-fuse capacitor has a first terminal coupled to the second terminal of the read selection transistor, and a second terminal coupled to a low voltage control line.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

Abstract: A hardware forwarding element is provided that includes a group of unit memories, a set of packet processing pipelines, and an error signal fabric. Each packet processing pipeline includes several of match action stages. Each match action stage includes a set of match action tables stored in a set of unit memories. Each unit memory is configured to detect an error in the unit memory and generate an error output when an error is detected in the memory unit. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing match tables into a first bit in the error signal fabric. The error signal fabric, for each match action stage, combines error outputs of the unit memories storing action tables into a second bit in the error signal fabric.

Abstract: A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

Abstract: A display device includes: a display unit including scan lines, data lines, unit areas corresponding to intersections of the scan lines and the data lines, the unit areas including first unit areas in an effective display area, second unit areas in a dummy area around the effective display area, some of the second unit areas being smaller than the first unit areas, and pixels in the first unit areas; a timing controller configured to receive first data including image data corresponding to the first and second unit areas and to convert the first data into second data corresponding to the effective display area; and a data driver configured to generate a data signal corresponding to the second data. The display unit includes a first horizontal line having fewer pixels than the number of the data lines.

Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.

Abstract: An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element.

Abstract: Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.

Abstract: The consumption current of a TCAM device is reduced. A semiconductor device includes multiple sub-arrays each including a TCAM cell array. Each sub-array searches the corresponding part of the input search data. Each sub-array outputs the search result indicative of a match for every entry without searching, when the corresponding first control signal is activated.