Patents Examined by Connie Yoha
  • Patent number: 10068916
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Patent number: 10056385
    Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: August 21, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 10050196
    Abstract: Phase change memory materials in a dielectric-doped, antimony-rich GST family of materials which are antimony rich relative to GST-225, are described that have speed, retention and endurance characteristics suitable for storage class data storage A memory device includes an array of memory cells, where each memory cell includes a first electrode and a second electrode coupled to a memory element. The memory element comprises a body of phase change memory material that comprises a combination of Ge, Sb, and Te with a dielectric additive in amounts effective to provide a crystallization transition temperature greater than to 160° C., greater that 170° C. in some effective examples and greater than 190° C. in other effective examples. A controller is coupled to the array, and configured to execute set operations and reset operations for memory cells in the array.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 14, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Huai-Yu Cheng, Hsiang-Lan Lung
  • Patent number: 10032525
    Abstract: A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: July 24, 2018
    Assignee: SK hynix Inc.
    Inventor: Jong Yeol Yang
  • Patent number: 10032498
    Abstract: A memory cell unit and a recurrent neural network including memory cell units are provided. The memory cell unit includes a first time gate configured to control a cell state value of the memory cell unit, based on a phase signal of an oscillatory frequency, and a second time gate configured to control an output value of the memory cell unit, based on the phase signal.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: July 24, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., UNIVERSITAET ZUERICH
    Inventors: Daniel Neil, Shih-Chii Liu, Michael Pfeiffer
  • Patent number: 10032503
    Abstract: A semiconductor memory device including a weak cell storage circuit suitable for programming therein weak cell information, and outputting the weak cell information in an initialization operation; a cell array region including a first cell region which stores the weak cell information received from the weak cell storage circuit, in the initialization operation; a refresh address generation block suitable for generating a refresh address by counting a refresh signal, and outputting a weak cell address corresponding to the weak cell information outputted from the first cell region, as the refresh address, with a predetermined cycle; and a refresh circuit suitable for performing a refresh operation for a word line corresponding to the refresh address, among a plurality of word lines.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: July 24, 2018
    Assignee: SK Hynix Inc.
    Inventors: Kyeong-Pil Kang, Sung-Soo Chi
  • Patent number: 10026472
    Abstract: In a multi-port memory, a first pulse signal generator circuit generates a first pulse signal following input of a clock signal. A first latch circuit sets a first start signal to a first state in response to generation of the first pulse signal, and resets the first start signal to a second state in response to a first delayed signal obtained by delaying the first start signal by a delay circuit. A second pulse signal generator circuit generates a second pulse signal following input of the first delayed signal. A first latch circuit sets a second start signal to the first state and holds this state in response to generation of the second pulse signal, and resets the second start signal to the second state in response to a second delayed signal obtained by delaying the second start signal by the delay circuit. The memory operates based on start signals.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichiro Ishii
  • Patent number: 10008268
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Gou Fukano
  • Patent number: 9947384
    Abstract: A semiconductor device may be provided. The semiconductor device may include a target address storage circuit and a first row address generation circuit. The target address storage circuit may be configured to count the number of times that blocks are selected by a plurality of logic level combinations of an address based on an active pulse. The target address storage circuit may be configured to store and output the address of a target block, which is selected at least a predetermined number of times, among the blocks as a target address. The first row address generation circuit may be configured to generate a first row address, which is counted, from the target address based on a first internal command.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: April 17, 2018
    Assignee: SK hynix Inc.
    Inventor: Dong Yoon Ka
  • Patent number: 9941013
    Abstract: A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 9934463
    Abstract: Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: April 3, 2018
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Jae-sun Seo, Shimeng Yu, Yu Cao, Sarma Vrudhula
  • Patent number: 9922721
    Abstract: An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 20, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hyun Min Song
  • Patent number: 9905298
    Abstract: A nonvolatile memory device includes a common source line connected to a plurality of cell strings. The cell strings each include a first selection transistor coupled to a string selection line, a second selection transistor coupled to a ground selection line, and a plurality of memory cells coupled to a plurality word-lines. The second selection transistors are commonly coupled to the common source line. A method of operating the nonvolatile memory device includes receiving a program command and an access address, and performing a program operation on a selected page according to the access address while floating the common source line. The common source line is floated based on at least one of the program command and the access address.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sang-Hyun Joo
  • Patent number: 9905281
    Abstract: Provided herein are a data input/output circuit and a semiconductor memory system having the same. The data input/output circuit may be coupled to an input/output line. The data input/output circuit may include a data input unit and a data output unit. The data input unit may deliver input data, inputted through the input/output line, to a page buffer during a data input period. The data output unit may deliver output data, outputted from the page buffer, to the input/output line during a data output period. The data input unit may include a signal reception unit coupled to the input/output line and configured to receive the input data from the input/output line; and a data delivery unit configured to deliver the input data inputted to the signal reception unit to the page buffer during the data input period.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: February 27, 2018
    Assignee: SK hynix Inc.
    Inventor: Yong Gu Kang
  • Patent number: 9899093
    Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic controls the peripheral circuit to perform a verify operation during the program operation and then apply a pre-drain select line voltage to drain select lines of the selected memory block and unselected memory blocks.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: February 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jong Won Lee, Jin Su Park, Hyun Su Woo
  • Patent number: 9870808
    Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunui Lee, Won-joo Yun, Hye-seung Yu, In-dal Song
  • Patent number: 9858979
    Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Scott James Derner, Christopher John Kawamura, Charles L. Ingalls
  • Patent number: 9852781
    Abstract: An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: December 26, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Emanuele Confalonieri, Giuseppe Russo, Luca Porzio
  • Patent number: 9852803
    Abstract: A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 26, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Vinh Quang Diep, Liang Pang, Ching-Huang Lu, Yingda Dong
  • Patent number: 9847127
    Abstract: A memory device includes a sense amplifier coupled to a first read voltage during a first phase of a read operation and a second read voltage during a second phase of the read operation. A first and second bias voltages are based on the first and second read voltages and corresponding current on a bit line. A first capacitor includes a terminal coupled to the first and second bias voltages. A first amplifier includes an input coupled to another terminal of the first capacitor and another input coupled to a common mode voltage during the first phase and to a reference voltage during the second phase. A second capacitor includes a terminal coupled to an output of the first amplifier. A second amplifier includes an inverting input coupled to another terminal of the second capacitor and another input coupled to a common mode voltage.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 19, 2017
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Michael A. Sadd