Patents Examined by Connie Yoha
  • Patent number: 9558801
    Abstract: A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 31, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Hirotaka Takeno, Akio Yamamoto
  • Patent number: 9558827
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 31, 2017
    Assignee: SK Hynix Inc.
    Inventors: Moon Sik Seo, Kyung Sik Mun
  • Patent number: 9552887
    Abstract: A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwanghoon Kim, Jun Jin Kong, Changkyu Seol, Hong Rak Son
  • Patent number: 9548126
    Abstract: A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 17, 2017
    Inventor: Darryl G. Walker
  • Patent number: 9536614
    Abstract: A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 3, 2017
    Assignee: NXP USA, Inc.
    Inventors: Gilles J. Muller, Ronald J. Syzdek
  • Patent number: 9530504
    Abstract: A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes using a four-pass programming technique to program a block of the non-volatile memory cells.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Bo Lei, Gerrit Jan Hemink, Masaaki Higashitani, Jun Wan, Zhenming Zhou
  • Patent number: 9520177
    Abstract: A semiconductor device is equipped with memory cells which are provided at the intersections of word lines and local bit lines, hierarchical switches which are respectively connected between the local bit lines and a global bit line, and a hierarchical sense amplifier which amplifies a potential difference generated between signal nodes, with the signal nodes being respectively connected to the local bit lines. According to the present invention, because the hierarchical sense amplifier is a differential type circuit, a stable sensing operation can be performed. In addition, because one hierarchical sense amplifier can be assigned to multiple local bit lines, the number of hierarchical sense amplifiers can be reduced.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: December 13, 2016
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventors: Yasuhiro Matsumoto, Kyoichi Nagata, Izumi Nakai
  • Patent number: 9508436
    Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 29, 2016
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 9490027
    Abstract: An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyun Min Song
  • Patent number: 9478283
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 25, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Reiji Mochida, Kazuyuki Kouno
  • Patent number: 9460784
    Abstract: A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. The current source supplies a first current. A reference memory cell is coupled to the current source at a reference node. The reference memory cell has a select device comprising a chalcogenic semiconductor material. A clamp circuit is coupled between the reference memory cell and a second power supply. The clamp circuit is configured to control a second current such that when the first current and second current are substantially equal, the reference voltage generated at the reference node tracks a threshold voltage of the select device.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 4, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Patent number: 9455044
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program pulse applying operation and a verify operation on the memory cell array, a pass/fail check circuit performing a pass/fail check operation on a program operation including the program pulse applying operation and the verify operation, and a control logic controlling the peripheral circuit and the pass/fall check circuit to perform the pass/fail check operation during the program pulse applying operation.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 27, 2016
    Assignee: SK Hynix Inc.
    Inventor: Byoung In Joo
  • Patent number: 9450575
    Abstract: A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: September 20, 2016
    Assignee: SK hynix Inc.
    Inventor: Byoung-Chan Oh
  • Patent number: 9449683
    Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: September 20, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Andrea Redaelli, Fabio Pellizzer
  • Patent number: 9437258
    Abstract: Provided is a data readout circuit capable of, even when a high voltage is applied during data read-out operation, preventing erroneous writing of the data and reading out the data correctly. The data readout circuit includes: a non-volatile storage element; a latch circuit including: an input inverter; an output inverter; and a MOS transistor; a first MOS transistor connected between the non-volatile storage element and the latch circuit; a second MOS transistor connected between the latch circuit and the first power supply terminal; a first bias circuit configured to bias a gate of the first MOS transistor; and a second bias circuit configured to bias the MOS transistor in the latch circuit, each of the first bias circuit and the second bias circuit being configured to output a predetermined bias voltage when the data in the non-volatile storage element is read out.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 6, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Makoto Mitani, Kotaro Watanabe
  • Patent number: 9431090
    Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 30, 2016
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 9431114
    Abstract: A method of operating a semiconductor device includes dividing an operation of the semiconductor device into a plurality of periods, and determining a plurality of state codes respectively corresponding to the periods; performing the operation according to a received command; when a pause command is received, pausing the operation and storing a state code of the plurality of state codes corresponding to a paused period among the plurality of periods; and performing the operation starting from a period determined according to the stored state code when a resumption command is received.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: August 30, 2016
    Assignee: SK Hynix Inc.
    Inventor: Tai Kyu Kang
  • Patent number: 9424909
    Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: August 23, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Niladri Narayan Mojumder, Ping Liu, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
  • Patent number: 9412453
    Abstract: An operating method of a memory system which includes a nonvolatile memory device including memory cells connected to a plurality of word lines, the operating method including pre-charging a selected one of the plurality of word lines; detecting a variation in a voltage or a current on the selected word line after the selected word line is floated; generating runtime failure information according to the detected variation; and determining a state of the selected word line or a state of a memory block including the selected word line, based on the runtime failure information.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Hee Choi, Daeseok Byeon, Byunggil Jeon
  • Patent number: 9406391
    Abstract: Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 2, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong, Wei Zhao