Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.

Abstract: A ridge structure (7) including at least a light-absorbing layer (4) is provided on a semiconductor substrate (1). A semiconductor embedding layer (8) has a refractive index lower than that of the light-absorbing layer (4) and embeds a side surface of the light-absorbing layer (4). A semiconductor layer (13) has a refractive index between that of the light-absorbing layer (4) and that of the semiconductor embedding layer (8) and is provided between the side surface of the light-absorbing layer (4) and the semiconductor embedding layer (8). The refractive index of the semiconductor layer (13) is n3, a wavelength of the incident light (15) is ?, a thickness of the semiconductor layer (13) in a lateral direction is in a range of ?30% to +20% of ?/(4×n3).

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.

Abstract: A method of manufacturing customized ceramic labial/lingual orthodontic brackets by digital light processing, said method comprises measuring dentition data of a profile of teeth of a patient, wherein measuring dentition data is performed using a CT scanner or intra-oral scanner, based on the dentition data, creating a three dimensional computer-assisted design (3D CAD) model of the patient's teeth using reverse engineering, and saving the 3D CAD model on a computer, designing a 3D CAD bracket structure model for a single labial or lingual bracket structure, importing the 3D CAD bracket structure model into a Digital Light Processing (DLP) machine, directly producing the bracket by layer manufacturing.

Abstract: The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.

Abstract: Disclosed are a display panel and a display device. The display panel comprises: a base substrate, a plurality of scanning lines, a first insulating layer, a plurality of data lines, an interlayer insulating layer, and an auxiliary power line. The auxiliary power line comprises: a plurality of sub-auxiliary power lines and a plurality of auxiliary conduction lines; the plurality of sub-auxiliary power lines are arranged in a first direction and extend in a second direction, and two sub-auxiliary power lines that are at least partially adjacent are electrically connected by means of at least one auxiliary conduction line; the orthographic projection of at least one of the plurality of auxiliary conduction lines on the base substrate does not overlap the orthographic projections of the scanning lines on the base substrate.

Abstract: A transistor includes an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and provided between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode. The semiconductor layer is embedded in the tubular gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.

Abstract: A display device includes a pixel in a display area. The pixel includes: spaced apart first and second electrodes; a first insulating layer on the first electrode and the second electrode and between the first electrode and the second electrode and having a first etch selectivity; a first insulating pattern on the first insulating layer between the first electrode and the second electrode, and having a second etch selectivity; a light emitting element on the first insulating pattern; a second insulating pattern having the second etch selectivity and being on one area of the light emitting element such that a first end and the second end of the light emitting element are exposed; and third and fourth electrodes configured to electrically connect the first end and the second end of the light emitting element to the first and second electrodes, respectively.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, multiple sub-pixels, multiple data lines, a test circuit, multiple data leads, at least one test pad, and at least one first test signal line. The multiple data lines are electrically connected to the multiple sub-pixels, and configured to provide data signals to the multiple sub-pixels. The multiple data leads are electrically connected to the multiple data lines and the test circuit. At least one test pad is located on at least one side of the test circuit. The at least one first test signal line is electrically connected to at least one test pad and the test circuit, and includes at least two conductive layers connected in parallel and electrically connected to each other.

Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

Abstract: An electronic device A1 of the present disclosure includes an electronic component 1, a support member (die pad portion 21 of a lead frame 2) including a mount surface (obverse surface 211) carrying the electronic component 1, and a bonding material 3 provided between the electronic component 1 and the support member (die pad portion 21) for fixing the electronic component 1 to the support member (die pad portion 21). The mount surface (obverse surface 211) includes a first region 211a where a plurality of grooves 711 are formed and a second region 211b that surrounds the first region 211a as viewed in the z direction. The bonding material 3 is in contact with the first region 211a, and is not in contact with the second region 211b. This configuration serves to achieve an improvement in the reliability of the electronic device.

Abstract: A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 ?m; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 ?m. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

Abstract: Feedback generation for a container load process includes digitizing a manual workflow into stages, assigning intermediate targets to each stage, monitoring the workflow, and generating notifications to exert feedback control over the workflow.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes receiving a workpiece that includes a first gate structure disposed over a first active region, a second gate structure disposed over a second active region, a first gate spacer extending along a sidewall of the first gate structure and disposed at least partially over a top surface of the first active region, a second gate spacer extending along a sidewall of the second gate structure and disposed at least partially over a top surface of the second active region, and a source/drain feature. The method also includes treating a portion of the first gate spacer and a portion of the second gate spacer with a remote radical of hydrogen or oxygen, removing the treated portions, and after the removal, depositing a metal fill material over the source/drain feature.

Abstract: A display substrate, a method for manufacturing the same and a display device. In the display substrate, a sealant region includes: a corner sealant region, a lead-in sealant region, and a first sealant region on a first side of a display area. The corner sealant region is provided with an encapsulation base layer. A non-display area is provided with a second power line, a gate drive circuit and multiple first signal lines configured to provide signals to the gate drive circuit. The second power line includes a power line corner portion and a first power line portion, the first power line portion overlaps the first sealant region, and the first power line portion extends in a first direction. A target portion of each first signal line is at least located in the corner sealant region.

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

Abstract: Various embodiments relate generally to data science and data analysis, computer software and systems, and control systems to provide a platform to facilitate implementation of an interface, and, more specifically, to a computing and data storage platform that implements specialized logic to facilitate distribution of items in accordance with an automatically adaptive schedule, for example, via an interface. In some examples, a method may include predicting data representing, for example, a zone of time in which depletion of an item is predicted. The method may monitor whether to replenish the item, and transmit via a network an electronic message including one or more item characteristics associated with the item to be replenished. The method may also include receiving another electronic message, and transmitting a control message to a merchant computing system to initiate adaptive distribution to replenish the item, among other things.

Abstract: A layout of electrode pads on a front surface of a first semiconductor chip is different from a layout of them on a second semiconductor chip. An overall layout of the semiconductor chips mounted on the insulated substrate and the layouts of the electrode pads on the front surfaces of the semiconductor chips including the first and second semiconductor chips are determined so that a value of a resistance component and/or a value of a reactance component between each two electrode pads that are the same type respectively on different semiconductor chips and are connected in parallel become the same. As a result, current waveform oscillation between semiconductor devices fabricated on the semiconductor chips, respectively, may be suppressed.