Patents Examined by Courtney A. Bowers
  • Patent number: 5534713
    Abstract: A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: July 9, 1996
    Assignee: International Business Machines Corporation
    Inventors: Khaled E. Ismail, Frank Stern
  • Patent number: 5530273
    Abstract: In a semiconductor device which includes a semiconductor substrate, a collector region of a first conductivity type formed on the semiconductor substrate, a base region of a second conductivity type reverse to the first conductivity type, an emitter region of the first conductivity type formed within the base region, an intermediate semiconductor layer of the second conductivity type is formed within the collector region, an additional semiconductor layer of the first conductivity type is superposed on the intermediate semiconductor layer, and the base region is overlaid on the additional semiconductor layer.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: June 25, 1996
    Assignee: NEC Corporation
    Inventor: Satoshi Nakamura
  • Patent number: 5530262
    Abstract: Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: June 25, 1996
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, Kent E. Morrett, Michael D. Potter, Matthew J. Rutten
  • Patent number: 5525819
    Abstract: A Concentric MESFET (CMESFET) is a small-signal traveling-wave transistor having a grounded source electrode which concentrically surrounds and shields the gate and drain electrodes from electromagnetic fields generated by other nearby circuit elements. S-parameters for the transistor are computed to obtain gain curves for design configurations. For a gate length of 2 um, maximum gain occurs with a gate width of 3.0 mm. The CMESFET has calculated bandwidth of 17 GHz for a 2 um gate length and a gate width of 300 m. Coupling capacitance between device electrodes and a nearby transmission line are calculated and used to verify improved source electrode shielding isolation of the device from interference and crosstalk originating in surrounding circuits.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: June 11, 1996
    Assignee: The Aerospace Corporation
    Inventor: Allyson D. Yarbrough
  • Patent number: 5525822
    Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300.ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600.ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: June 11, 1996
    Assignee: Thunderbird Technologies, Inc.
    Inventor: Albert W. Vinal
  • Patent number: 5523595
    Abstract: A semiconductor device having a ferroelectric film or a polycrystalline silicon gate, a humidity-resistant hydrogen barrier film, like TiN film, TiON film, etc., formed by hydrogen non-emission film forming method over the ferroelectric film or the polycrystalline silicon gate.
    Type: Grant
    Filed: May 6, 1994
    Date of Patent: June 4, 1996
    Assignee: Ramtron International Corporation
    Inventors: Kazuhiro Takenaka, Akira Fujisawa
  • Patent number: 5521419
    Abstract: A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.
    Type: Grant
    Filed: October 21, 1994
    Date of Patent: May 28, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Wataru Wakamiya, Shinichi Satoh, Hiroji Ozaki, Takahisa Eimori, Yoshinori Tanaka
  • Patent number: 5519244
    Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: May 21, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
  • Patent number: 5517047
    Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: May 14, 1996
    Assignee: Harris Corporation
    Inventors: Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller, William H. Speece
  • Patent number: 5517038
    Abstract: Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: May 14, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Hirotada Kuriyama
  • Patent number: 5514879
    Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 7, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5510633
    Abstract: A porous silicon Light Emitting Diodes (LEDs) device and method for fabricating LEDs with supporting circuits on a silicon chip or wafer for a Full Width Array in which a switch diode structure is used to form the porous silicon LED element and later drives the LED after the LED is fabricated. The LED is formed by defining an area in the switch diode for placing an LED element. Epi silicon is deposited in the defined area; and the epi silicon is electrochemical etched to produce porous silicon. This procedure creates column-like Si structures of nanometer dimension which can efficiently emit visible to infrared light at room temperature. Next, the porous silicon LED chip can be cut and butted without excessive damage. In this way, the chips bearing both LEDs and drive circuitry are made of silicon and can be cut and accurately butted by known techniques to form a low cost, high resolution Full Width LED array.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: April 23, 1996
    Assignee: Xerox Corporation
    Inventors: Thomas E. Orlowski, Sophie V. Vandebroek
  • Patent number: 5508541
    Abstract: A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: April 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Masami Aoki, Takeshi Hamamoto
  • Patent number: 5506437
    Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.
    Type: Grant
    Filed: May 24, 1993
    Date of Patent: April 9, 1996
    Assignee: Inmos Limited
    Inventors: Michael D. May, Jonathan Edwards, David L. Waller
  • Patent number: 5504348
    Abstract: A thin film transistor array comprises an insulative substrate, a plurality of pixel electrodes arranged in a matrix on the insulative substrate, a plurality of thin film transistors connected respectively to the pixel electrodes, a plurality of address lines formed on the insulative substrate, each address line being connected to a plurality of control electrodes of the thin film transistors, and a plurality of data lines arranged on the insulative substrate in such a manner as to intersect the address lines, each data line being connected to a plurality of data input electrodes of the thin film transistors. A short-wiring is formed on the outside of a display region on the insulative substrate on which the pixel electrodes are arranged, and the short-wiring is connected to at least two of the address lines and the data lines by a two-terminal element having non-linear resistance characteristics defining voltage/current characteristics on the basis of a space charge limited current.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: April 2, 1996
    Assignees: Casio Computer Co., Ltd., Oki Electric Industry Co., Ltd.
    Inventors: Mamoru Yoshida, Makoto Sasaki, Hiroyuki Okimoto, Tsutomu Nomoto, Shunichi Sato
  • Patent number: 5502329
    Abstract: A protection monolithic semiconductor component has an input terminal, an output terminal and a reference terminal. The component includes between the input terminal and output terminal, a first diode of a first polarity having a low forward dissipation and a reverse breakdown voltage ranging from 20 to 40 volts; and, between the output terminal and reference terminal, a second protection diode having the same polarity. The first diode is laterally disposed between two electrodes of the front surface of the component, and the second diode is vertically disposed between an electrode on the front surface of the component and an electrode on the rear surface.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: March 26, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 5498907
    Abstract: A plurality of power semiconductor switching devices are included in a circuit module in a pattern whereby interconnecting lead lengths are minimized to provide improved circuit characteristics and to insure uniform current sharing when said devices are paralleled during switch-on, switch-off and steady state conditions.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: March 12, 1996
    Assignee: Allied Signal Inc.
    Inventors: John J. Tumpey, Sampat Shekhawat, Gayton L. Silvestro, John J. Brogle
  • Patent number: 5498888
    Abstract: A semiconductor device having a source region, a drain region, a channel region between the source region and the drain region, a gate consisting of at least three input electrodes provided above the channel region, and a potential modulating film provided between the channel region and the gate. The potential modulating film can assume at least two potential modulating states, so that the potential of the channel region is modulated between and held at different values. The potential of the channel region is modulated by changing the state of the potential modulating film. Specifically, the potential of the channel region is modulated by not only applying voltages to the input electrodes but also controlling the state of the potential modulating film.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: March 12, 1996
    Assignee: Rohm Co., Ltd.
    Inventor: Takanori Ozawa
  • Patent number: 5497015
    Abstract: A semiconductor device using interference effects of electron waves passing through a multichannel, wherein the multichannel is formed by a Dirac-delta-doped layer. A method of manufacturing a semiconductor device comprising the steps of: selectively forming a region of a predetermined crystallographic orientation onto a semiconductor substrate; and alternately growing the first semiconductor layer and the second semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer onto the region of the predetermined crystallographic orientation by a vapor-phase growth method so as to have a convex shape in a manner such that an area of an upper layer is smaller. A semiconductor device in which a channel portion comprising a zigzag fine line is provided between a source and a drain.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: March 5, 1996
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Kenji Funato, Yoshifumi Mori
  • Patent number: 5495124
    Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.
    Type: Grant
    Filed: October 26, 1993
    Date of Patent: February 27, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima