Patents Examined by Courtney G McDonnough
  • Patent number: 11965923
    Abstract: The present disclosure is directed to self-tests for electrostatic charge variation sensors. The self-tests ensure an electrostatic charge variation sensor is functioning properly. The self-tests may be performed while an electrostatic charge variation sensor is active and without interruption to the application employing the electrostatic charge variation sensor.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 23, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Fabio Passaniti, Daniele De Pascalis, Enrico Rosario Alessi
  • Patent number: 11959982
    Abstract: A low-cost modular liquid nitrogen low-temperature multi-nuclear magnetic resonance probe includes a Dewar, a pluggable coil and a front-end gain amplifier. The Dewar includes a cylindrical sandwich chamber, the center of the cylindrical sandwich chamber constitutes a room-temperature chamber, a sandwich of the cylindrical sandwich chamber is divided into a vacuum chamber and a liquid nitrogen chamber by a liquid nitrogen vessel wall, the vacuum chamber is located between the room-temperature chamber and the liquid nitrogen chamber, the pluggable coil and the front-end gain amplifier are provided in the vacuum chamber, the pluggable coil comprises a coil portion and a pluggable base, the coil portion is in pluggable connection with the pluggable base, and the pluggable coil is connected with the front-end gain amplifier. The probe realizes the transmission of radio frequency pulses and the reception of magnetic resonance signals, and is applicable to whole-body imaging of a small animal.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 16, 2024
    Assignee: INNOVATION ACADEMY FOR PRECISION MEASUREMENT SCIENCE AND TECHNOLOGY, CAS
    Inventors: Zhi Zhang, Qingjia Bao, Chaoyang Liu, Xinjie Liu, Fang Chen, Jiaxin Wang, Xin Cheng, Maili Liu
  • Patent number: 11953554
    Abstract: A remote control device testing environment evaluates operational performance of physical implementations of remote control devices. This operational performance of the physical implementations of the remote control devices allows the integrated circuits of the remote control devices as well as integrated circuit interfaces electrically coupling these integrated circuits to each other to be evaluated. Additionally, the interconnection, such as electrical coupling to provide an example, between these integrated circuits and/or the integrated circuit interfaces can be evaluated which otherwise would not be evaluated by software simulation alone. Moreover, the evaluating of this operational performance of the physical implementations of the remote control devices allows these remote control devices to be in evaluated in a real world environment with exposure to various environmental factors, such as temperature, humidity, and/or electromagnetic interference to provide some examples.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: April 9, 2024
    Assignee: CSC Holdings, LLC
    Inventors: Heitor J. Almeida, Bowen Song, John Markowski
  • Patent number: 11946983
    Abstract: A current transformer includes a housing including generally cylindrical outer and inner walls defining an internal chamber, a front face enclosing one end of the internal chamber, a base, and a central opening defined by the inner wall. A generally toroidal current transformer core is disposed within the internal chamber. A secondary wiring is disposed about the transformer core and is configured to generate a current in response to magnetic flux in the transformer core. A pin housing is disposed on the front face of the housing adjacent the base. The pin housing has electrically conductive pins. A test wire passes through the central opening. The secondary wiring is electrically connected to a first pair of the pins and the test wire is electrically connected to a second pair of the pins.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 2, 2024
    Assignee: ABB Schweiz AG
    Inventors: Chandrashekar Nagawaram, Cecil Rivers, Jr.
  • Patent number: 11946968
    Abstract: According to an aspect, there is provided a method for self-diagnosing a mobile device comprising at least one or more actuators, one or more sensors and a display. The method comprises, first, feeding a pre-defined control signal to a first actuator of the mobile device and measuring, in response to the feeding, a first electric signal using a first sensor of the one or more sensors. Then, the first electric signal is compared to one or more reference signals associated with the first actuator and the pre-defined control signal. If the first electric signal fails to match the one or more reference signals according to one or more pre-defined criteria, a negative diagnosis is indicated to a user of the mobile device using one or more of a display of the mobile device and one or more actuators of the mobile device.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 2, 2024
    Assignee: BLANCCO TECHNOLOGY GROUP IP OY
    Inventors: Timo Sairiala, Sami Gerdt, Markku Valtonen
  • Patent number: 11933084
    Abstract: A presence detection sensor for unlocking an opening panel of a motor vehicle, said sensor comprising a microcontroller implementing an analog-digital converter and comprising a first input, a second input forming the voltage reference of said analog-digital converter, a third input for supplying the microcontroller with voltage, and a plurality of inputs-outputs, and a capacitive voltage divider connected to at least one of the inputs-outputs of the plurality of inputs-outputs. The sensor comprises a resistive module connected between the first input and the second input of the microcontroller and a capacitive module connected between the second input of the microcontroller and a ground.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 19, 2024
    Assignee: VITESCO TECHNOLOGIES GMBH
    Inventors: Olivier Elie, Gabriel Spick
  • Patent number: 11935797
    Abstract: A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 19, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaodong Luo
  • Patent number: 11927626
    Abstract: In an inspection device, the reference signal output section is connected to an external power supply device in electrical parallel with a semiconductor sample, and outputs a reference signal according to the output of the external power supply device. The removal processing section performs, based on the reference signal, processing for removing a noise component, which is due to the output of the external power supply device from the current signal output from the semiconductor sample and outputs a processing signal. The electrical characteristic measurement section measures the electrical characteristics of the semiconductor sample based on the processing signal. The processing signal is subjected to the removal processing performed based on the reference signal from the reference signal output section for which the value of the gain has been set by the gain setting section.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 12, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Toshiki Yamada
  • Patent number: 11921156
    Abstract: A structure and method for the wafer level testing of interposer-based photonic integrated circuits is described that includes the formation of an upturned mirror structure and the method of utilizing the interposer-based mirror structure for electrical and optical testing of optoelectrical circuits that include emitting components such as lasers, detecting components such as photodetectors, and both emitting and detecting components. Electrical activation of the optoelectrical emitting or sending devices and the subsequent detection and measurement of the optical signals in detecting or receiving devices provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 5, 2024
    Inventors: Lucas Soldano, Jing Yang, Yong Meng Lee, Suresh Venkatesan
  • Patent number: 11913895
    Abstract: To easily detect a crack having occurred in a steel material. A current measurement device measures a value of a current flowing through a target steel material that is immersed in an electrolyte aqueous solution and applied with tensile stress while subjected to hydrogen charging, and a device for detecting the occurrence of a crack or the like uses the measured current value to determine the occurrence of a crack in the target steel material when the amount of change in the current flowing through the target steel material, the change rate of the amount of change in the current, or the change rate of the change rate of the amount of change in the current exceeds a threshold value.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: February 27, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yosuke Takeuchi, Takuya Kamisho, Masamitsu Watanabe
  • Patent number: 11914004
    Abstract: A monitoring system for sensing electrical parameters including current and voltage can comprise a current transformer and an antenna. The current transformer can be configured to sense current passing through a conductor. The antenna can be configured to sense electrical potential of the conductor by sensing an electric field generated by the conductor. The antenna can sense the electrical potential independent of whether current is present in the conductor. The monitoring system can further comprise a temperature sensor configured to sense a temperature of the conductor. A sensing module can include a housing supporting the current transformer, the antenna, and the temperature sensor for monitoring an electrical power circuit.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 27, 2024
    Assignee: ANORD MARDIX (USA) INC.
    Inventor: Alan H. Katz
  • Patent number: 11906569
    Abstract: A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 20, 2024
    Assignee: SHOWA DENKO K.K.
    Inventors: Koichi Murata, Isaho Kamata, Hidekazu Tsuchida, Akira Miyasaka
  • Patent number: 11906579
    Abstract: A method for the testing of optoelectronic chips which are arranged on a wafer and have electrical interfaces in the form of contact pads and optical interfaces which are arranged to be fixed relative thereto in the form of optical deflection elements, e.g., grating couplers, with a specific coupling angle. The wafer is adjusted in three adjustment steps with one of the chips relative to a contacting module such that the electrical interfaces of the chip and contacting module contact one another, and the optical interfaces of the chip and contacting module occupy a maximum position of the optical coupling.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: February 20, 2024
    Assignee: JENOPTIK GmbH
    Inventors: Tobias Gnausch, Armin Grundmann, Thomas Kaden, Norik Janunts, Robert Buettner, Christian Karras
  • Patent number: 11899060
    Abstract: In an optical carrier injection method, a pulsed optical beam having pulse duration of 900 fs or lower is applied on a backside of a substrate of an integrated circuit (IC) wafer or chip, and is focused at a focal point in an active layer on a frontside of the substrate. Photons of the optical beam are absorbed at the focal point by nonlinear optical interaction(s) to inject carriers. The pulsed optical beam may be applied using a fiber laser in which the fiber is doped with Yb and/or Er. An output signal may be measured, comprising an electrical signal or a light output signal produced by the IC wafer or chip in response to the injected carriers. By repeating the applying, focusing, and measuring over a grid of focal points in the active layer, an image of the IC wafer or chip may be generated.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: February 13, 2024
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Thomas F. Kent, Jeffrey A. Simon
  • Patent number: 11883331
    Abstract: A welding helmet can record a welding time based on an arc intensity detected by a sensor mounted on the helmet. A configured level is compared with the arc intensity detected by the sensor to determine a welding duration. Individual welding times from multiple welding instances can be accumulated over a period of time to provide a total welding time for an operator. The total welding time may be stored in the welding helmet.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 30, 2024
    Assignee: LINCOLN GLOBAL, INC.
    Inventors: Paul H. Rumpke, Richard D. Smith, Bruce J. Chantry
  • Patent number: 11862266
    Abstract: The present disclosure provides a chip detection method and a chip detection apparatus. The chip detection method includes: providing a chip to be tested, the chip including a power pump region, and the power pump region including a plurality of power pump structures; detecting a dim light signal emitted from the power pump region when the chip is in a preset working mode; and determining whether the dim light signal matches a corresponding power pump working mode in the preset working mode, and if not, confirming that the power pump region has a defect, the power pump working mode including a working state of the power pump structures in the power pump region.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jianbo Zhou
  • Patent number: 11860225
    Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fukumi Unokuchi, Toshitsugu Ishii
  • Patent number: 11862495
    Abstract: The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: He Zhu
  • Patent number: 11852673
    Abstract: Provided is a method for generating a chip probing wafer map, and the method includes: obtaining test data associated with a first chip, wherein the first chip includes a plurality of sequentially arranged first dies, and each of the first dies belongs to one of a plurality of bin numbers; assigning different predetermined color codes to the bin numbers; and generating a first general chip probing wafer map for the first chip by assigning a color code of each of the first dies as a corresponding predetermined color code according to the bin number to which each of the first dies belongs.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: December 26, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Ju Wu, Ching-Ly Yueh
  • Patent number: 11852667
    Abstract: A device for determining an effective piezoelectric coefficient of a thin film of a material of a sample, includes a source of x-rays incident on the sample; a detector of x-rays diffracted by the sample; a device for positioning the x-ray source and the x-ray detector with respect to the sample; a voltage source making contact with the sample; a device for controlling the voltage source so as to apply an electric field to the sample during an electrical cycle, the electric field generating a strain of the sample and a stress on the sample; a device for measuring a diffraction peak of the x-rays as a function of the electric field applied to the sample during the electrical cycle; a processing device configured to determine the piezoelectric coefficient.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: December 26, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Nicolas Vaxelaire