Abstract: A virtual storage system according to an aspect of the present invention includes multiple storage systems each including: a storage controller that accepts a read/write request for reading or writing from and to a logical volume; and multiple storage devices. The storage system defines a pool that manages the storage device capable of allocating any of storage areas to the logical volume, and manages the capacity (pool capacity) of the storage areas belonging to the pool, and the capacity (pool available capacity) of unused storage areas in the pool. Furthermore, the storage system calculates the total value of the pool available capacities of the storage systems included in the virtual storage system, and provides the server with the total value as the pool available capacity of the virtual storage system.

Abstract: Techniques provide for data deduplication. Such techniques involve: allocating a storage area in a storage device, the storage area including a first storage segment for storing an incompressible data block and a second storage segment for storing a compressed data block, a first size of the first storage segment being greater than a second size of the second storage segment; in response to receiving a write request, determining whether data block to which the write request is related is compressible; in response to determining that the data block is incompressible, adding header information to the data block to generate a first data segment of the first size; and storing the first data segment in the first storage segment through a deduplication operation. Accordingly, such techniques can increase the flexibility and efficiency of data deduplication.

Abstract: A memory system includes a memory controller and M memory chips. The memory controller generates a first data signal having one of 2M voltage levels different from each other, where M is a natural number greater than or equal to two, and outputs the first data signal through a first channel. The first data signal represents first data including M bits. The M memory chips are commonly connected to the memory controller through the first channel. When the M memory chips have an enabled state, the M memory chips simultaneously receives the first data signal transmitted through the first channel from the memory controller, and simultaneously obtains the M bits included in the first data based on the first data signal. Each of the M memory chips obtains a respective one of the M bits, and operates based on the respective one of the M bits.

Abstract: Methods, apparatuses, and systems related to data management and security in a memory device are described. Data may be stored in a memory system, and as part of an operation to move data from one region to another in the memory system, the data may be validated using one or more hash functions. For example, a memory device may compute a hash value of some stored data, and use the hash value to validate another version of that stored data in the process of writing the other version stored data to a region of the memory system. The memory device may store another hash that is generated from the hash of the stored data and a record of transactions such that transactions are identifiable; the sequence of transactions within the memory system may also be identifiable. Hashes of transactions may be stored throughout the memory system or among memory systems.

Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

Abstract: Techniques for managing storage may comprise: receiving a request for a first amount of free capacity, wherein the request includes a first priority denoting a purpose for which the first amount of free capacity is requested; determining whether a current utilization of storage exceeds a first threshold associated with the first priority; responsive to determining the current utilization of storage is less than the first threshold associated with the first priority, performing first processing including: determining whether there is a sufficient amount of existing free capacity to grant the first amount; and responsive to determining there is a sufficient amount of existing free capacity to grant the first amount, granting the first amount of free capacity; and responsive to determining the current utilization of storage is not less than the first threshold associated with the first priority, rejecting the request and not granting the first amount of free capacity.

Abstract: A memory comprising a memory array, including a plurality of blocks, and control circuits comprising logic to execute operations is provided. The operations include decoding a read setup burst command identifying (i) an address of a first read setup block in a set of read setup blocks and (ii) a number of read setup blocks, as candidates for read setup operations. The operations further including, in response to the decoding of the read setup burst command, performing a read setup burst operation on a plurality of read setup blocks of the set of read setup blocks.

Abstract: An apparatus comprises at least a first storage node of a plurality of storage nodes of a distributed storage system. The first storage node comprises a processor coupled to a memory. The first storage node is configured to receive from a host device a read operation directed to a particular portion of a logical address space of the storage system, where the logical address space is divided among the storage nodes. The first storage node is further configured to determine that the read operation is potentially part of a stream of multiple read operations directed to respective particular portions of the logical address space, and to send, to at least a second one of the storage nodes, an indication of the determination made by the first storage node. The stream of multiple read operations may comprise a sequential read stream directed to respective contiguous portions of the logical address space.

Abstract: The disclosed technology relates determining a first subset of a plurality drives having a first zone size and a second subset of the plurality of drives having a second zone size different from the first zone size, within a redundant array of independent disks (RAID) group. A prevailing zone size between the first zone size and the second zone size is determined. One or more logical zones within the determined first subset of the plurality of drives and the determined second subset of the plurality of drives for a received input-output operation is reserved based on the determined prevailing zone size. The received input-output operation is completed within the reserved one or more logical zones within the determined first subset of the plurality of drives and the determined second subset of the plurality of drives.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. It may be identified whether the I/O request is eligible for handling via a first path without also requiring handling via a second path. If the I/O request is eligible, the I/O request may be processed via the first path on a host I/O stack without processing the I/O request via the second path on a storage array I/O stack. If the I/O request is ineligible, the I/O request may be processed via the first path on the host.

Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing data on a memory controller. One of the methods comprises obtaining a first request and a second request to access respective data corresponding to the first and second requests at a first memory device of the plurality of memory devices; and initiating interleaved processing of the respective data; receiving an indication to stop processing requests to access data at the first memory device and to initiate processing requests to access data at a second memory device, determining that the respective data corresponding to the first and second requests have not yet been fully processed at the time of receiving the indication, and in response, storing, in memory accessible to the memory controller, data corresponding to the requests which have not yet been fully processed.

Abstract: Method and apparatus for performing an operation are described. A method includes choosing at least one primary logical hierarchical data space. The at least one primary logical hierarchical data space may have a plurality of subdivisions. The method may further include determining at least one subdivision of the at least one primary logical hierarchical data space. The method may further include choosing at least one secondary logical hierarchical data space. The at least one secondary logical hierarchical data space may have a plurality of subdivisions. The method may further include determining at least one subdivision of the at least one secondary logical hierarchical data space. The method may further include performing at least one operation corresponding to the at least one subdivision of the at least one primary logical hierarchical data space.

Abstract: Systems and methods for making a cross-site storage solution resilient towards mediator unavailability are provided. According to one embodiment, a stretched storage system is operable to bring a mediator associated with a primary and secondary distributed storage system back into the role of an arbitrator for peered consistency groups (CGs). A mediator reseed status indicator is maintained for multiple CGs to identify when the mediator's status information for a CG is stale. When the mediator becomes available and a local CG is identified as the subject of a mediator reseed process, the master node of the primary that hosts a master copy of a dataset for the local CG performs the reseed process, including: (i) causing relationship status information for the local CG to be updated on the mediator to the current state maintained by the primary; and (ii) resetting the mediator reseed status indicator.

Abstract: A virtual storage volume that includes storage space on potentially many different physical disks may be implemented as one or more chunks. This allows for dynamic volume storage adjustment. Dynamic volume storage adjustment allows for increasing volume size without moving data unnecessarily. In addition, dynamic volume storage adjustment also allows freeing up storage space in a node with minimum movement of data.

Abstract: Distributed storage systems are implemented with rule based rebalancing mechanisms. Methods includes steps for creating a set of rules for rebalancing data storage space in a storage node cluster, as well as steps for performing a rebalance operation across the storage node cluster using the set of rules. The distributed storage systems include one or more labels for storage pools and storage volumes.

Abstract: A method for hierarchical workload allocation in a storage system, the method may include determining to reallocate a compute workload of a current compute core of the storage system; wherein the current compute core is responsible for executing a workload allocation unit that comprises one or more first type shards; and reallocating the compute workload by (a) maintaining the responsibility of the current compute core for executing the workload allocation unit, and (b) reallocating at least one first type shard of the one or more first type shards to a new workload allocation unit that is allocated to a new compute core of new compute cores.

Abstract: Method for active data storage management to optimize use of an electronic memory. The method includes providing signal injections for data storage. The signal injections can include various types of data and sizes of data files. Response signals corresponding with the signal injections are received, and a utility of those signals is measured. Based upon the utility of the response signals, parameters relating to storage of the data is modified to optimize use of long-term high latency passive data storage and short-term low latency active data storage.

Abstract: A storage control node receives data to be written to a striped volume, allocates first and second stripes, writes the data to at least one data strip of the first stripe, computes parity data based on the data written to the first stripe, and writes the parity data to the first stripe. The storage control node sends a copy command to a target storage node which comprises the at least one data strip of the first stripe to thereby cause the at least one data strip to be copied to a data strip of the second stripe which resides on the target storage node. The storage control node writes additional data to the second stripe, computes updated parity data based on the additional data and the parity data of the first stripe, writes the updated parity data the second stripe, and releases the first stripe for reuse.

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.