Patents Examined by Craig Thompson
  • Patent number: 7101813
    Abstract: A dielectric film containing atomic layer deposited Zr—Sn—Ti—O and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing titanium and oxygen onto a substrate surface by atomic layer deposition, depositing zirconium and oxygen onto a substrate surface by atomic layer deposition, and depositing tin and oxygen onto a substrate surface by atomic layer deposition form the Zr—Sn—Ti—O dielectric layer. Dielectric films containing atomic layer deposited Zr—Sn—Ti—O are thermodynamically stable such that the Zr—Sn—Ti—O will have minimal reactions with a silicon substrate or other structures during processing.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: September 5, 2006
    Assignee: Micron Technology Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7056763
    Abstract: The invention relates to a composite structure for electronic microsystems and a method for producing this composite structure, with the composite structure being provided with a polycrystalline diamond layer (4) for heat withdrawal. The growth substrate (1) contains or forms a component layer (2) with the electronic microsystems, which are provided with binary or higher order component compound semiconductors. A protective layer (3), which encloses the component layer at least indirectly almost entirely, is placed between the component layer 2 and the diamond layer (4). A material is selected for the protective layer whose reactivity with the precursor materials present in the deposition of the diamond layer (4) by means of CVD, preferably by means of plasma CVD, is smaller than that of the component layer (2), and said protective layer.
    Type: Grant
    Filed: August 31, 2002
    Date of Patent: June 6, 2006
    Assignee: Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.
    Inventors: Herbert Güttler, Peter Koidl, Matthias Seelmann-Eggebert
  • Patent number: 7056764
    Abstract: An electronic sensor device has at least one sensor component, which bears on a bearing base of a rewiring structure. Contact areas of the sensor component are electrically conductively connected to contact pads of the rewiring structure. External contact areas of the rewiring structure are led outward from a housing for the electrical contact-connection of the electronic sensor device. A method is also described for producing the electronic sensor device.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: June 6, 2006
    Assignee: Infineon Technologies AG
    Inventors: Albert Auburger, Bernd Stadler, Stefan Paulus, Horst Theuss
  • Patent number: 7041533
    Abstract: One or more stabilizers are disposed on the surface of a semiconductor device component prior to bonding the same to a higher-level substrate. Upon assembly of the semiconductor device component face-down upon a higher-level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher-level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher-level substrate to maintain a substantially parallel relation therebetween. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher-level substrate. The stabilizers may be preformed structures or fabricated on the surface of the semiconductor device component, such as by way of a stereolithographic method.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Syed Sajid Ahmad
  • Patent number: 7037755
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 2, 2006
    Assignee: Ziptronix, Inc.
    Inventor: Paul M. Enquist
  • Patent number: 7026171
    Abstract: A rapid thermal annealing (“RTA”) process providing for an RTA equipment is disclosed. The RTA equipment has a pyrometer providing for measuring an operation parameter, e.g., a temperature of the RTA process. The RTA process comprises steps of proceeding a first RTA step to a wafer in the RTA equipment, then comparing a measured value of the operation parameter with a reference range of value of the operation parameter, thereafter proceeding a second RTA step to the wafer in the RTA equipment when the measured value of the operation parameter is in between the reference range of value of the operation parameter. When the measured value of the operation parameter is out of the reference range of value of the operation parameter, the RTA equipment is turned off, and the wafer is unloaded from the RTA equipment and loaded into another RTA equipment to complete the RTA process.
    Type: Grant
    Filed: July 4, 2003
    Date of Patent: April 11, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Y. Y. Chang, Shih-Liang Chou, L. H. Lee, Tsung-De Lin, Kou-Yow Tseng, Wen-Cheng Lien
  • Patent number: 7022599
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes depositing an O3-TEOS oxide film having a good flow-like property under a high adhesive force in order to prevent degradation in the characteristic of the surface of a lower insulating film made of a PE-TEOS oxide film and generation of defect due to the topology difference. Therefore, the disclosed method can improve the electrical characteristic of a semiconductor device and the manufacturing yield.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 4, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyong Sik Yoo, Sung Ki Park
  • Patent number: 7023031
    Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: April 4, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Richard H. Tsai
  • Patent number: 7012321
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 14, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Patent number: 7005755
    Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
  • Patent number: 6998322
    Abstract: Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: February 14, 2006
    Assignee: Cree, Inc.
    Inventors: Mrinal Kanti Das, Lori A. Lipkin, John W. Palmour, Scott Sheppard, Helmut Hagleitner
  • Patent number: 6998334
    Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: February 14, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, James M. Wark, David R. Hembree, Syed Sajid Ahmad, Michael E. Hess, John O. Jacobson
  • Patent number: 6998656
    Abstract: A double-injection field-effect transistor has an anode, a cathode, a substantially transparent channel, a substantially transparent gate insulator, and at least one substantially transparent gate electrode. The transistor may also have a substantially transparent anode and/or cathode. The transistor may also be formed on a substantially transparent substrate. Electrode contacts and electrical interconnection leads may also be substantially transparent. Methods for making and using such double-injection field-effect transistors are also disclosed.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: February 14, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Randy Hoffman
  • Patent number: 6998326
    Abstract: The method for manufacturing a shallow trench isolation (STI) in a semiconductor device with an enhanced gap-fill property and without a detrimental effect of fluorine by introducing a two-stage thermal process. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming a trench structure in the semiconductor substrate; forming a hydrogen (H2)-based high density plasma (HDP) oxide layer over a first resultant structure; forming a nitrogen trifluoride (NF3)-based HDP oxide layer into the trench structure with a predetermined depth; carrying out a two-stage thermal process for removing fluorine in the NF3-based HDP oxide layer; and forming a helium (He)-based HDP oxide layer over a second resultant structure.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 14, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Hong Kim
  • Patent number: 6995083
    Abstract: Disclosed is a method for producing an electrical and/or mechanical connection between at least two flexible thin-film substrates, referred to as flexible substrates hereinafter as well as a corresponding contact arrangement. The invention is distinguished by the to-be-joined flexible substrates, which each are provided with at least one opening at the point of connection being positioned in such a manner that the opening of one flexible substrate is congruent with the opening of another flexible substrate, by a bonding element being positioned on both sides of each congruently aligned opening, and by both the bonding elements being joined to a bonding connection by being pressed against each other and at least partially enclosing the peripheral edges of the openings facing said bonding elements.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: February 7, 2006
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Werner Haberer, Martin Schuttler, Hans-Jorg Beutel
  • Patent number: 6992018
    Abstract: Methods are described for depositing a film or discontinuous layer of discrete clusters, of material (e.g., metals, metal mixtures or alloys, metal oxides, or semiconductors) on the surface of a substrate, e.g., a patterned silicon wafer, by i) dissolving a precursor of the material into a supercritical or near-supercritical solvent to form a supercritical or near-supercritical solution; ii) exposing the substrate to the solution, under conditions at which the precursor is stable in the solution; and iii) mixing a reaction reagent into the solution under conditions that initiate a chemical reaction involving the precursor, thereby depositing the material onto the solid substrate, while maintaining supercritical or near-supercritical conditions. The invention also includes similar methods for depositing material particles into porous solids, and films of materials on substrates or porous solids having material particles deposited in them.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: January 31, 2006
    Assignee: University of Massachusetts
    Inventors: James J. Watkins, Jason M. Blackburn, David P. Long, Jason L. Lazorcik
  • Patent number: 6992026
    Abstract: A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: January 31, 2006
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu, Naoki Uchiyama, Toshimitsu Wakuda
  • Patent number: 6992017
    Abstract: A process for cleaning a silicon surface. First, a silicon surface is cleaned with an oxidant solution. Next, the silicon surface is rinsed with HF vapor or liquid and then with the silicon surface with hydrogen water or deionized water under megasonic agitation. Finally, the silicon surface is cleaned with an oxidant solution a second time. The present inventive cleaning process can be applied in thin film transistor (TFT) fabrication and the TFT obtained has higher electron mobility.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: January 31, 2006
    Assignee: AU Optronics Corp.
    Inventors: Chia-Tien Peng, Ming-Wei Sun
  • Patent number: 6984529
    Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: January 10, 2006
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: George Stojakovic, Rajiv M. Ranade, Ihar Kasko, Joachim Neutzel, Keith R. Milkove, Russell D. Allen, Kim Poong Mee Lee, legal representative, Young Hoon Lee, deceased
  • Patent number: 6985363
    Abstract: To provide a card-type recording medium which is capable of increasing memory capacity and excellent in rigidity and shock resistance, and to provide a method for manufacturing the same. A card-type recording medium comprising a memory module 221, 222, 270 which is so constituted that a plurality of memory chips 15 are mounted on a memory board 21, 22, 70, 63, 65 is mounted on one surface of a base board 10, and an IC chip 13, 14, 60 for controlling operation of the plurality of memory chips is mounted on the other surface of the base board, with all housed in a package 30, 31.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 10, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Yagi, Kazuhiro Uji, Michiro Yoshino, Kenichi Yamamoto