Abstract: A semiconductor module includes a circuit substrate composed of a wiring pattern, an electrical insulating layer and a thermal radiation board, and in use is fixed to an external thermal radiation member, in which the electrical insulating layer is composed of a thermal conductive mixture containing 70-95 wt % of an inorganic filler and 5-30 wt % of a thermosetting resin. A warping degree of the circuit substrate with respect to the external thermal radiation member is at most 1/500 of a length of the substrate, and the circuit substrate warps to protrude toward the thermal radiation board as the temperature rises. Accordingly, the thermal radiation property does not deteriorate even when the temperature rises in use. At a time of fixing the circuit substrate to the external thermal radiation member, the thermal resistance is kept to be a sufficiently low level.

Abstract: The invention includes a capacitor construction. A capacitor electrode has a perovskite-type dielectric material thereover. The perovskite-type dielectric material has an edge region proximate the electrode, and a portion further from the electrode than the edge region. The portion has a different amount of crystallinity than the edge region. The invention also includes a method of forming a capacitor construction. A capacitor electrode is provided, and a perovskite-type dielectric material is chemical vapor deposited over the first capacitor electrode. The depositing includes flowing at least one metal organic precursor into a reaction chamber and forming a component of the perovskite-type dielectric material from the precursor. The precursor is exposed to different oxidizing conditions during formation of the perovskite-type dielectric material so that a first region of the dielectric material has more amorphous character than a second region of the dielectric material.

Abstract: A method of making organic memory devices containing organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The organic memory devices are made using a patternable, photosensitive dielectric that facilitates formation of the memory cells and mitigates the necessity of using photoresists.

Abstract: An electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the first surface, at least one electrical contact disposed on the flexible elevation, and a conduction path disposed on the surface or in the interior of the flexible elevation between the electrical contact and the electronic circuit. A method for producing the electronic component is also provided.

Abstract: A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.

Abstract: An electronic component is produced by incorporating a sacrificial part in a plastic housing shape. After molding, the sacrificial part is etched out or otherwise removed from the completed plastic housing. As a result, channels and/or cavities can be formed in the plastic housing in order to allow access to sensor areas on the semiconductor chip.

Abstract: A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

Abstract: A method for fabricating a high-density ferroelectric memory device is disclosed in which a plug can be heat-treated at a high temperature. The method includes the following. Forming an interlayer dielectric film on a semiconductor substrate after forming a transistor on the semiconductor substrate. The interlayer dielectric film is selectively etched to form a contact hole. A plug and a barrier film are buried into the contact hole. A conductive film is formed on the interlayer dielectric film including the barrier film. The conductive film is selectively etched to make both ends of the conductive film inclined so as to form a capping layer for capping the barrier film. There are sequentially formed a lower electrode, a ferroelectric thin film and an upper electrode upon the interlayer dielectric film (which includes the capping layer).

Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: A dam or barrier around the periphery of a die in a flip-chip package changes the shape of the underfill to reduce stress resulting from edge effects. The dam can include a treated region of a substrate having an affinity to an underfill material. The treated region causes liquid underfill material to bead, thereby controlling the wetting angle of the underfill material and shaping the underfill to eliminate sources of stress such as underfill fillet regions that are subject to significant shrinkage. The dammed underfill additionally avoids or reduces the extent of areas having thermal coefficients of expansion that differ from the optimal level because of low filler particle concentration.

Abstract: A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop Si1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed.

Abstract: A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

Abstract: A method of manufacturing a semiconductor device having self-aligned contact structure with side wall spacers and offset nitride films. The method includes forming the side wall spacers as having lower side wall spacers that are composed of silicon oxide films and that are in contact with lower sides of gate electrode side walls, and as having upper side wall spacers that are composed of silicon nitride films and that are in contact with upper sides of the gate electrodes side walls. A distance is thus formed between the device substrate and an interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurence of poor contact.

Abstract: A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whi

Abstract: The present invention provides a plasma processing apparatus and processing method capable of maintaining a constant processing profile.

Abstract: A method for producing silicon nitride and silicon oxynitride films by CVD technology, where even at lower temperatures, acceptable film-deposition rates are achieved, without the by-product production of large amounts of ammonium chloride.

Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.