Patents Examined by Craig Thompson
  • Patent number: 6922217
    Abstract: In an amorphous silicon thin film transistor-liquid crystal display device and a method of manufacturing the same, gate patterns including a gate line and a gate electrode are formed on an insulation substrate having a display region and a driving circuit region on which a plurality of shift registers are formed, a gate insulating film, active layer patterns and data patterns including source and drain electrodes are formed successively on the substrate, a passivation layer on the substrate has a first contact hole exposing a drain electrode of the display region and second and third contact holes respectively exposing a gate electrode and source and drain electrodes of a first transistor of each of the shift registers, an electrode patterns on the passivation layer include a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode to the source and drain electrodes of the first transistor through the second and
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: July 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Gyu Kim
  • Patent number: 6921718
    Abstract: A semiconductor device includes a semiconductor substrate and an electrode disposed on a major surface of the semiconductor substrate. A via hole is formed on a center of the electrode so as to open from a surface of the electrode to a place under the surface of the semiconductor substrate. A via-hole foundation electrode for inhibiting diffusion from a metal layer is formed inside the via hole and on the surface of the electrode, a via-hole electrode is formed on the surface of the via-hole foundation electrode. A back via hole is formed on the back of the semiconductor substrate opposite to the major surface thereof, and opened from the back of the semiconductor substrate to the via-hole electrode. A back via-hole electrode is formed on the back of the semiconductor substrate including the inside of the back via hole.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: July 26, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoto Andoh, Takao Ishida, Kenji Hosogi
  • Patent number: 6921672
    Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: July 26, 2005
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: Akella V. S. Satya, Gustavo A. Pinto, David L. Adler, Robert Thomas Long, Neil Richardson, Kurt H. Weiner, David J. Walker, Lynda C. Mantalas
  • Patent number: 6921914
    Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: July 26, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
  • Patent number: 6921978
    Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
  • Patent number: 6919578
    Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: July 19, 2005
    Assignee: Ovonyx, Inc
    Inventors: Tyler A. Lowrey, Charles H. Dennison
  • Patent number: 6917054
    Abstract: A semiconductor device includes a trench formed on a source side of a drift region, a p-type gate region and a gate formed at the bottom of the trench, and the source formed over the entire surface of the unit device through an insulating film. The narrowest portion of a channel of the device is deeper than one-half the junction depth of the p-type gate region. This allows the width of the channel on the drain side to be reduced even when a lower energy ion implantation manufacturing process is used.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: July 12, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hidekatsu Onose, Hideo Homma, Atsuo Watanabe
  • Patent number: 6916726
    Abstract: A method for forming scribed grooves on a wafer and an apparatus for implementing the method. The method moves the cutting part such that its cutting edge forms an inverted trapezoid-shaped path, thereby reducing the scribing angle of the cutting edge to an acute angle. Consequently, the stress produced by the mechanical shock at the time of the scribing can be dispersed in the moving direction of the cutting edge and in a direction perpendicular to the surface of the wafer. The horizontal movement of the scribing cutting edge in the wafer enables the application of a sufficient load in a direction perpendicular to the scribing plane in the wafer. Consequently, vertical cracks are sufficiently generated, and the amount of dimensional deviation between the scribed groove and the cleaved plane is reduced. This method can produce chips featuring outside dimensions with higher precision and cleaved surfaces with high-quality mirror finish.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: July 12, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuji Ohno, Hiroshi Imai, Yoshito Nakase
  • Patent number: 6917550
    Abstract: A semiconductor memory device includes a pair of bit lines; a first sense amplifier coupled to the pair of bit lines; and a first controller, which controls the first sense amplifier. The first sense amplifier includes a flip-flop circuit having a pair of NMOS transistors and a pair of PMOS transistors; a first transistor connected to a source terminal of the NMOS transistors in the flip-flop circuit; and a second transistor connected to a source terminal of the PMOS transistors in the flip-flop circuit. The first controller includes a first NOR circuit, having input terminals to which a write command signal and a sense amplifier driving signal are supplied and having an output terminal connected to a gate of the first transistor.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: July 12, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masakuni Kawagoe, Akihiro Narumi
  • Patent number: 6916690
    Abstract: A method of fabricating polysilicon film is described. An amorphous silicon layer is formed on the substrate, an optical layer is formed on the amorphous silicon layer, wherein the optical has a first region having a first thickness and a second region having a second thickness, and the reflectivity of the first region for an excimer laser is higher than that of the second region. A laser annealing process is then preformed to transform the amorphous silicon layer into a polysilicon film.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: July 12, 2005
    Assignee: Au Optronics Corporation
    Inventor: Mao-Yi Chang
  • Patent number: 6917111
    Abstract: A method for fabricating cell plugs of a semiconductor device with cell plugs is disclosed, which increases the operation speed of the semiconductor device by reducing the cell plug resistance of the device. The semiconductor device includes a first insulating interlayer on a semiconductor substrate; a first cell plug on the semiconductor substrate through the first insulating interlayer; a second insulating interlayer on the first insulating interlayer; a silicide contact on a predetermined surface of the first cell plug through the first insulating interlayer; and a second cell plug on the silicide contact through the second insulating interlayer.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: July 12, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yoon Jik Lee, Jeong Tae Kim
  • Patent number: 6917085
    Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: July 12, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geum-Jong Bae, Nae-In Lee, Hwa-Sung Rhee, Young-Gun Ko, Tae-Hee Choe, Sang-Su Kim
  • Patent number: 6916678
    Abstract: A method for modifying a surface of a substrate to be processed, by utilizing plasma includes the steps of adjusting a temperature of the substrate from 200° C. to 400° C., introducing gas including nitrogen atoms or mixture gas including inert gas and the gas including nitrogen atoms into a plasma process chamber, adjusting pressure in the plasma process chamber above 13.3 Pa, generating plasma in the plasma process chamber, and injecting ions equal to or smaller than 10 eV in the plasma into the substrate to be processed.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: July 12, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kitagawa, Nobumasa Suzuki, Shinzo Uchiyama
  • Patent number: 6916674
    Abstract: The present invention discloses a method for fabricating multiple-thickness insulator layers via strain field generated by stress. The strain field is used for alternating a develop mechanism of insulator layers on the quantum dots. By forming the multiple-thickness insulator layers at various developing rates, not only leakage current is prevented, but also components are kept isolated in the nano-electronics components. In nano-electronics manufacturing, the method for fabricating multiple-thickness insulator layers results in both better product reliability and the yield rate. It is potential for integral circuit manufacturing.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: July 12, 2005
    Assignee: Industrial Technology Research Institute
    Inventors: Pang-Shiu Chen, Buo-Chin Hsu, Chee-Wee Liu
  • Patent number: 6914264
    Abstract: A GaN semiconductor stack layer is formed on top of a substrate for manufacturing a light emitting diode. The GaN semiconductor stack layer includes, from the bottom up, an N-type GaN contact layer, a light emitting stack layer and a P-type contact layer. The next step is to form a digital transparent layer on the P-type GaN contact layer, then use dry etching technique to etch downward through the digital transparent layer, the P-type GaN contact layer, the light emitting layer, the N-type GaN contact layer, and form an N-metal forming area within the N-type GaN contact layer. The next step is to form a first ohmic contact electrode on the P-type contact layer to serve as P-type ohmic contact, and a second ohmic contact electrode on the N-metal forming area to serve as N-type ohmic contact. Finally, a bump pad is formed on the first ohmic contact electrode and the second ohmic contact electrode, respectively.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: July 5, 2005
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Lung-Chien Chen, Wen-How Lan, Fen-Ren Chien
  • Patent number: 6913948
    Abstract: A Ball Grid Array package having an increased fatigue life and improved conductive pad adhesion strength, as well as providing sufficient wiring space within the package, is disclosed. In particular, solder joints having a combination of mask-defined and pad-defined solder joint profiles are formed using a mask having non-circular elongated openings. The non-circular elongated openings of the mask have a major axis and a minor axis, such that the dimension of the openings along the major axis is greater than the diameter of the conductive pads, and the dimension of the openings along the minor axis is less than the diameter of the conductive pads. In addition, the major axis of the openings within the mask are selectively oriented in the direction of highest stress for each solder joint within the package, while providing ample wiring space therein.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: July 5, 2005
    Assignee: International Business Machines Corporation
    Inventors: David V. Caletka, Eric A. Johnson
  • Patent number: 6914256
    Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 5, 2005
    Assignee: North Carolina State University
    Inventors: Zhibo Zhang, Veena Misra, Salah M. A. Bedair, Mehmet Ozturk
  • Patent number: 6913947
    Abstract: A multi-layer circuit board is manufactured by laminating and bonding together a plurality of resin films, on each of which a circuit pattern is directly drawn by injecting ink. The ink includes metal particles, having a diameter in the order of nanometers, dispersed therein. At the same time when the laminated resin films are bonded together under pressure and heat, the metal particles in the ink are sintered, thereby forming a solid electrical circuit printed on the resin film. Since the circuit pattern is directly drawn on the resin film, the process of manufacturing the multi-layer circuit board is simplified.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: July 5, 2005
    Assignee: Denso Corporation
    Inventor: Masashi Totokawa
  • Patent number: 6914328
    Abstract: An electronic component and a method of producing it, with at least one insulating layer is encompassed by the invention. The insulating layer includes a polymer including norbornene monomers. The polymer retains a double ring structure of the monomer C7H10 while there is breaking of a carbon double bond of the norbornene monomer. This breaking of the carbon double bond is created by a homopolymerization of the monomers to form crosslinked norbornene monomers with polar fluorocarbon bonds.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: July 5, 2005
    Assignee: Infineon Technologies AG
    Inventor: Alfred Haimerl
  • Patent number: 6913957
    Abstract: A method of fabricating a thin film transistor array substrate is described. A gate and a scan line electrically connected to the gate are formed on a substrate. A gate insulating layer is formed over the substrate. A patterned channel layer and a patterned ohmic contact layer are formed on the gate insulating layer above the gate. A transparent conductive layer and a metal layer are formed and patterned to define a source/drain region, a data line and a pixel region. A passivation layer exposing the metal layer on the pixel region is formed over the substrate. The metal layer exposed by the passivation layer is removed to expose the transparent conductive layer on the pixel region, using the passivation layer as a photomask, so as to form a pixel electrode. Since the process only needs four photomasks, the process cost can be reduced.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: July 5, 2005
    Assignee: Quanta Display Inc.
    Inventor: Ko-Chin Yang