Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

Abstract: A semiconductor device includes: element isolation regions; a projecting semiconductor region; a plurality of first gate electrodes each formed on both side surfaces and a top surface of a portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between a pair of opposed end portions of the element isolation regions and being component elements of a plurality of transistors; at least one second gate electrode formed between the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and applied with a voltage for turning off the transistor.

Abstract: A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.

Abstract: A semiconductor device includes trench gate structures that extend from a first surface into a semiconductor body of silicon carbide. The trench gate structures include a gate electrode and are spaced apart from one another along a first horizontal direction and extend into a body region with a longitudinal axis parallel to the first horizontal direction. First sections of first pn junctions between the body regions and a drift structure are tilted to the first surface and parallel to the first horizontal direction. Source regions form second pn junctions with the body regions. A gate length of the gate electrode along a second horizontal direction orthogonal to the first horizontal direction is greater than a channel length between the first sections of the first pn junctions and the second pn junctions.

Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n? type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: A light emitting device (LED) package includes: a substrate having a loading surface, a mounting surface and a pair of concave portions formed at both ends of the substrate, wherein each of the concave portions has an inner surface intersecting both of the loading surface and the mounting surface; metal wirings including a pair of electrodes, which covers a portion of the loading surface and the mounting surface and the inner surface, and a conductive part disposed on the loading surface; an LED chip loaded on the conductive part; a housing having a side wall surrounding the LED chip and a supporting surface facing the loading surface; and a covering member which is disposed on the loading surface and has a closing portion overlapping at least a portion of the concave portions when viewed from above, wherein at least a portion of the supporting surface is fixed to the closing portion.

Abstract: A light emitting assembly comprising a solid state device, when and if coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first wavelength radiation, and an enveloping vessel enhancing the luminescence of the solid-state device and providing a mechanism for arranging luminophoric medium in receiving relationship to said first, radiation, and which in exposure to said first radiation, is excited to responsively emit second wavelength radiation or to otherwise transfer its energy without radiation to a third radiative component. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is converted to achromatic light without hue by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors on the walls of the solid-state light envelope which keeps the diode and the fluorescers and phosphors under a vacuum or a rare or Noble gas.

Abstract: Provided are light emission devices including an output coupler and optical apparatuses having the same. The light emission device may include a QD layer containing quantum dots and a nano-antenna structure including an output coupler configured to control an output characteristic of light emitted from the QD layer. The output coupler may be configured to output an emission wavelength of the QD layer. The nano-antenna structure may include one of a metallic antenna, a dielectric antenna, and a slit-containing structure, or may have a multi-patch antenna structure or a fishbone antenna structure.

Abstract: An organic electroluminescence device includes a first electrode, a hole transport region on the first electrode, a light emitting layer on the hole transport region, an electron transport region on the light emitting layer, and a second electrode on the electron transport region. The electron transport region includes an electron transport layer directly on the light emitting layer. The electron transport layer includes a first ternary compound including a halogen element.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

Abstract: A semiconductor package may include a chip disposed on a substrate, a conductive structure disposed on the substrate to include a conductive structure frame including a side surface facing at least one side surface of the chip and to include conductive structure fingers extending from the conductive structure frame toward an edge of the substrate, and an electromagnetic interference (EMI) shielding layer covering the chip and the conductive structure and contacting a side surface of an end of one or more of the conductive structure fingers.

Abstract: An electroluminescence display device is disclosed, which may use a polysilicon thin film transistor and an oxide thin film transistor together by using a dual line with respect to a plurality of switching transistors arranged on the same line. The electroluminescence display device includes a first active layer; a first gate line arranged on the first active layer and intersecting the first active layer; a second active layer forming a channel different from that of the first active layer, arranged on the first gate line; and a second gate line arranged on the second active layer and intersecting the second active layer. The first gate line and the second gate line are overlapped with each other, and the first gate line and the second gate line supply the same gate signal.

Abstract: A vertical transient voltage suppression device includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second heavily-doped area having the first conductivity type, and a diode. The first doped well is arranged in the semiconductor substrate and spaced from the bottom of the semiconductor substrate, and the first doped well is floating. The first heavily-doped area is arranged in the first doped well. The second heavily-doped area is arranged in the semiconductor substrate. The diode is arranged in the semiconductor substrate and electrically connected to the second heavily-doped area through a conductive trace.

Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a first lower area provided on the semiconductor substrate, and including a plurality of magnetoresistive effect elements, a second lower area provided on the semiconductor substrate, and being adjacent to the first lower area, a first upper area provided above the first lower area, and including a first material film formed of an insulating material or a semiconductor material, and a second upper area provided above the second lower area, being adjacent to the first upper area, and including a second material film formed of an insulating material different from a material of the first material film.

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

Abstract: A semiconductor device package is provided, which includes a carrier, an emitter and a first transparent encapsulant. The carrier has a first surface. The emitter is disposed on the first surface. The first transparent encapsulant encapsulates the emitter. The first transparent encapsulant includes a body and a lens portion. The body has a first planar surface. The lens portion is disposed on the body and has a first planar surface. The first planar surface of the lens portion is substantially coplanar with the first planar surface of the body.