Abstract: A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric layer. A doped silicon semiconductor substrate is covered with variable thickness silicon oxide regions on the surface thereof with junctions between the variable thickness regions. The silicon oxide regions are substantially thicker beneath the center of the floating gate electrode. Source/drain regions formed in the substrate extend beneath the tunnel oxide regions with the junctions aligned with the regions. The floating gate electrodes formed over the silicon oxide regions above the source/drain regions including dielectric sidewalls within the floating gate electrode above the junctions. The variable thickness silicon oxide regions are tunnel oxide regions on either side of a gate oxide region.

Abstract: Floating gates of nonvolatile memory cells are formed in pairs within a pyramidal or truncated pyramidal opening in a semiconductor layer between a top surface thereof and a heavily doped source region spaced from the surface of the semiconductor layer. The floating gates control the conductance of channel regions formed along the sloped sidewalls of the pyramidal openings between surface drains and the buried source region.