Patents Examined by Cynthia Britt
  • Patent number: 11860228
    Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: January 2, 2024
    Assignee: XILINX, INC.
    Inventors: Albert Shih-Huai Lin, Niravkumar Patel, Amitava Majumdar, Jane Wang Sowards
  • Patent number: 11860224
    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: January 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11862269
    Abstract: A testing method for a packaged chip includes: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Cheng-Jer Yang
  • Patent number: 11852668
    Abstract: A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: December 26, 2023
    Assignee: OPTIMAL PLUS LTD.
    Inventors: Shaul Teplinsky, Arie Peltz, Dan Sebban
  • Patent number: 11856460
    Abstract: Reception of a frame is appropriately stopped. A communication system is a communication system that includes first and second information processing devices. The first information processing device performs control such that a signal (which is a signal having backward compatibility) serving as an index by which the second information processing device receiving a frame stops the reception of the frame is transmitted to the second information processing device. The second information processing device performs control such that the reception of the frame is stopped based on the signal (which is a signal having backward compatibility) serving as an index by which reception of the frame is stopped when the frame transmitted from the first information processing device is received.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 26, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Eisuke Sakai, Takeshi Itagaki, Kazuyuki Sakoda, Tomoya Yamaura
  • Patent number: 11852680
    Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: December 26, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Yuan Wen
  • Patent number: 11846673
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11836385
    Abstract: An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: December 5, 2023
    Assignee: fmad engineering kabushiki gaisha
    Inventor: Aaron Foo
  • Patent number: 11835581
    Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: December 5, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11838125
    Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The disclosure relates to encoding and decoding by using a polar code in a wireless communication system, and an operation method of a transmission-end apparatus includes determining segmentation and the number of segments, based on parameters associated with encoding of information bits, encoding the information bits according to the number of check bits, and transmitting the encoded information bits to a reception-end apparatus.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongsil Jeong, Min Jang
  • Patent number: 11829227
    Abstract: A method for configuring a storage circuit, including: writing data via an input line into the storage circuit by a software write access; writing a bit-wise inverted form of the data via the input line into the storage circuit by a subsequent software write access; and generating an error signal if a comparison based on the written data and the written bit-wise inverted form of the data indicates a storage circuit configuration error, wherein the storage circuit permits hardware read access and lacks software read access.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: November 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Veit Kleeberger, Rafael Zalman
  • Patent number: 11831441
    Abstract: The invention relates to an improved transmission protocol for uplink data packet transmission in a communication system. A receiver of a user equipment receives a Fast Retransmission Indicator, referred to as FRI. The FRI indicates whether or not a base station requests a retransmission of a previously transmitted data packet. A transmitter of the user equipment retransmits the data packet using the same redundancy version as already used for the previous transmission of the data packet.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: November 28, 2023
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Alexander Golitschek Edler von Elbwart, Ayako Horiuchi, Lilei Wang
  • Patent number: 11822822
    Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Thomas Vogelsang
  • Patent number: 11823756
    Abstract: A method and device for testing a memory array structure, and a non-transitory storage medium are provided. The method includes that: respective storage data corresponding to each preset test pattern is written into a to-be-tested memory array, the each preset test pattern being one of preset test patterns in a preset test pattern library; a row aggressing test is repeatedly performed on the to-be-tested memory array until a bit error occurs in the storage data, to obtain row aggressing test times, corresponding to the each preset test pattern, of the to-be-tested memory array, where the bit error characterizes that the storage data has changed; a target preset test pattern corresponding to the to-be-tested memory array is determined from the preset test pattern library based on the row aggressing test times; and an array structure of the to-be-tested memory array is determined based on the target preset test pattern.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 21, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jianbin Liu, Maosong Ma
  • Patent number: 11824557
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11816410
    Abstract: A system and method are disclosed for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: November 14, 2023
    Assignee: Siemens Electronic Design Automation Gmbh
    Inventors: Dominik Strasser, Jörg Grosse, Jan Lanik, Raik Brinkmann
  • Patent number: 11808810
    Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: November 7, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11811528
    Abstract: This application relates to the field of wireless communications technologies, and discloses an encoding method and apparatus, to improve accuracy of reliability calculation and ordering for polarized channels. The method includes: obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence includes sequence numbers of N polarized channels, the first sequence is same as a second sequence or a subset of the second sequence, the second sequence comprises sequence numbers of Nmax polarized channels, and the second sequence is the sequence shown in Sequence Q11 or Table Q11, K is a positive integer, N is a positive integer power of 2, n is equal to or greater than 5, K?N, Nmax=1024; selecting sequence numbers of K polarized channels from the first sequence; and performing polar code encoding on K the to-be-encoded bits based on the selected sequence numbers of the K polarized channels.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: November 7, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Wang, Gongzheng Zhang, Huazi Zhang, Chen Xu, Lingchen Huang, Shengchen Dai, Hejia Luo, Yunfei Qiao, Rong Li, Jian Wang, Ying Chen, Nikita Polianskii, Mikhail Kamenev, Zukang Shen, Yourui HuangFu, Yinggang Du
  • Patent number: 11809220
    Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: November 7, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Deepak Kumar Agarwal, Kunal Desai, Jimit Shah, Rakesh Gehalot
  • Patent number: 11808811
    Abstract: An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Kalyana Kantipudi, Niraj Vasudevan