Abstract: A system and method is provided for operation mode control. The system includes a mode controller generating a combination of electric potentials and an additional microprocessor having a storage module having a mode list, a detection module and a control module. The detection module detects the combination of the electric potentials and determines a shift direction of the mode controller according thereto. The control module selects a target operation mode adjacent to the current operation mode in the mode list according to the shift direction, and checks the disparity of the current operation mode and the target operation mode to generate a control signal to direct the computer system to reboot or execute an application specific to the second operation mode, and subsequently enables the computer system to operate in the second operation mode.

Abstract: A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.

Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Abstract: A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.

Abstract: Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LAB) of the addend in a dedicated circuit right at the beginning of the pipe. LAB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LAB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.

Abstract: A single bit FIR filter that minimizes computation time by pre-storing outputs or portions of outputs for accumulation and output.

Abstract: A method and apparatus for reducing the crest factor of a signal uses a plurality of partial correction signals having respective predetermined frequencies. For each of the partial correction signals, the following steps are performed: (a) determining a time position of a maximum absolute amplitude of the signal; (b) calculating an amplitude and a phase depending on said maximum absolute amplitude and said time position for the respective partial correction signal; and (c) subtracting the respective partial correction signal from said signal to obtain a partially corrected signal which is used as the signal in step (a) for the next of the plurality of partial correction signals, and going to step (a) for calculating the next partial correction signal. The last-obtained partially corrected signal is output as the reduced-crest factor signal.

Abstract: The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent. The data processing apparatus comprises processing logic providing multiple processing paths which are selectable to perform the data processing operation, including a first processing path operable to perform the data processing operation if a predetermined alignment condition exists. Further, at least one detector logic unit is provided which is operable to receive both the first exponent and the second exponent and to detect the presence of the predetermined alignment condition.

Abstract: A fast incrementer using zero detection and an increment method thereof. The incrementer performs a logic combination on an operand, first logic state inclusion information for each b-bit group of the operand, flag information for each b-bit group of the operand, and an increment value, and outputs a whole increment value for the operand.

Abstract: Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.

Abstract: There are provided efficient basis conversion matrices Dsd and Dds and a basis conversion method in a finite field GF(2n) using the basis conversion matrices for a case where a defining polynomial is a pentanomial, xn+xk(3)+xk(2)+xk(1)+1, and the exponents n, k(3), k(2), and (k1) satisfy the condition, n?k(3)>k(3)?k(1). In addition, an apparatus for the basis conversion in the finite field GF(2n) is provided. Since a pentanomial having a general form in an arbitrary degree is used as the defining polynomial, basis conversion between a standard representation and a dual representation is efficiently performed. Consequently, a dual basis multiplier can be efficiently implemented.

Abstract: Method, apparatus, and program means for performing misaligned memory load and copy using aligned memory operations together with a SIMD merge instruction. The method of one embodiment comprises determining whether a memory operation involves a misaligned memory address. The memory operation is performed with aligned memory accesses if the memory operation is determined as not involving a misaligned memory address. The memory operation is performed with an algorithm including a merge operation and aligned memory accesses if the memory operation is determined as involving a misaligned memory address.

Abstract: Apparatus and method for determining a fixed point in a mobile communication system are disclosed. An initial fixed point is set through simulation and a saturation for an output of a target device is compared with a reference saturation. Then, the position of the initial fixed point is adaptively changed according to the change in the output range of the target device. Therefore, when a floating point is converted into a fixed point, the performance of the system can be improved while the complexity of the hardware can be reduced.

Abstract: To perform multiplication of matrices in a vector processing system, partial products are obtained by dot multiplication of vector registers containing multiple copies of elements of a first matrix and vector registers containing values from rows of a second matrix. The dot products obtained from this dot multiplication are subsequently added to vector registers which form a product matrix. Each matrix can be divided into submatrices to facilitate the rapid and efficient multiplication of large matrices, which is done in parts by computing partial products of each submatrix. The matrix multiplication avoids rounding errors as it is bit-by-bit compatible with conventional matrix multiplication methods.

Abstract: In a method for performing a multiplication operation between a first operand and a second operand the multiplication operation is divided into at least two suboperations. At least one of the suboperations is performed in a time-interlaced manner, wherein the at least one suboperation is further divided into partial suboperations so that each partial suboperation is initiated at a different time.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: A system for frequency-domain scaling for DCT computation. Scale factors are applied to coefficients during the final steps of composition of 2-point DCTs. The number of multiplications and required precision are reduced. Fixed values for various scale factors can be computed and stored prior to executing the DCT so that performance can be improved. The fixed values are derived by knowing the length of the time-domain sequence. Some fixed values can be derived independently of the length of the time-domain sequence. The approach of the invention can also reduce the number of multiplications to compute the transform, and allow smaller bit-width sizes by reducing the number of required high-precision calculations.

Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

Abstract: A random number generator includes a chain of pairs of D-type flip-flops 205, 215 . . . having D and L inputs, a chain of substantially identical cascaded upper buffers 210,220 . . . each having a predetermined delay d1 and respective output taps. There is a chain of substantially identical cascaded lower buffers 240,260 . . . each having a predetermined delay d2, and respective output taps, wherein d1?d2. A first one of the pair of D-type flip flops 205 has its D and L inputs connected to a respective output tap of one of the upper buffers 210 and a respective output tap of one of the lower buffers 240, and a second one of the pair of D-type flip flops has its D and L inputs connected to a respective output tap of one of the lower buffers 260 and a respective output of one of the upper buffers 215. The common clock input 201 is connected to the first inputs of both the cascaded upper buffers and the cascaded lower buffers 210, 220 . . . and 240, 260 . . . A metastability detector 275,280 285,290,295 . . .

Abstract: A process for generating a serial number from a random number is suitable for being used on a device that uses serial number in a bus. First, this process generates a serial number for use from a random number according to a seed number, and then it checks if this generated serial number is repeated in the bus. When this generated serial number is the same as the serial number corresponding to any other devices that are of the same kind as the above mentioned device in the bus, a new serial number for use will be generated.