Abstract: A calculation speed of division carried out in a computer is increased. Partitioning means partitions a dividend y that is a 32-bit digital datum at every 8 bits from the least significant bit to generate four bit blocks y(1) to y(4). For the respective bit blocks, table reference means finds solutions z(1) to z(4) obtained by dividing, by a divisor x, values expressed by replacing the bits other than the bits in each bit block with 0, while referring to tables (1) to (4) stored in storage means. Addition means adds all the solutions z(1) to z(4) to find the solution z.
Abstract: Multi-functional digital signal processing (“DSP”) circuitry can perform any of a wide range of different DSP functions. For example, the DSP circuitry can perform multiplication of simple or complex numbers of different lengths. The multiplication of simple (i.e., non-complex) numbers can be augmented with addition of the resulting products. The DSP circuitry can also support implementing finite impulse response filters of either even or odd order.
Abstract: The present invention teaches a method for generating an output value corresponding to an input value via a first function comprising a first section and a second section with the use of a lookup table, comprising: prestoring a plurality of first sampling points corresponding only to a third section of a second function, wherein the second function further includes a fourth section and there is a first mathematical transformation between the first function and the second function; receiving the input value corresponding to the first section; generating the output value based on at least one of the first sampling points through performing the first mathematical transformation on the first sampling point; and outputting the output value.
Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.
Abstract: A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by ‘L?M’ data elements. A second operand having a second set of L data elements is shifted right by M data elements. The shifted first set is merged with the shifted second set to generate a resultant having L data elements.
Type:
Grant
Filed:
October 25, 2002
Date of Patent:
September 18, 2007
Assignee:
Intel Corporation
Inventors:
Julien Sebot, William W. Macy, Eric Debes, Huy V. Nguyen
Abstract: A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.
Abstract: A modular multiplication apparatus comprises a calculation unit which comprises processing units including a multiplier-adder unit and performs a modular multiplication by carrying out pipeline processes by the processing units; and a calculator configured to, before a first pipeline process, carry out a predetermined calculation for a processing result of one of the processing units in a pipeline process immediately before the first pipeline process, and when the first pipeline processes supply a calculation result of the predetermined calculation to a processing unit at an initial stage of the first pipeline process.
Abstract: There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed data are inputted wherein these data are selectively outputted in response to a control signal, a second selector to which another input data and an output data of a register are inputted wherein these data are selectively outputted in response to the control signal, an adder for receiving an output signal of the first selector and an output signal of the second selector to execute the addition of the output signals of the first and second selectors, and a register for receiving an output signal of the adder to hold the output signal in synchronization with a clock signal.
Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.
Abstract: An inverse filtering method, comprising: generating a first filtered signal based on an input signal; and combining the first filtered signal with the input signal for obtaining a residual signal. The generating comprises: generating at least two second filtered signals, each of said second filtered signals not significantly delayed in time relative to each other, the generating being stable and causal; and amplifying at least one of the second filtered signals with a prediction coefficient.
Abstract: A method for transposing data in a plurality of processing elements is comprised of a plurality of shifting operations and a plurality of storing operations. The shifting and storing operations are coordinated to enable data to be stored along a diagonal of processing elements from a first direction or first pair of directions and to be output from the diagonal in a second direction or a second pair of directions perpendicular to the first pair of directions, respectively. The plurality of storing operations are responsive to the processing elements' positions. The first and second pairs of directions are selected from among the dimensions of the array, e.g., the +x/?x, +z/?z and +y/?y pairs of directions.
Abstract: A device for and method of generating as many as K random bits by generating a first pseudo-random bit, generating a second pseudo-random bit, delaying the second pseudo-random bit a number of times, storing the delayed pseudo-random bits, and combining the first pseudo-random bit with each of the delayed second pseudo-random bits.
Type:
Grant
Filed:
March 3, 2004
Date of Patent:
August 28, 2007
Assignee:
The United States of America as represented by the Director National Security Agency
Abstract: Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit.
Type:
Grant
Filed:
February 17, 2004
Date of Patent:
August 21, 2007
Inventors:
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
Abstract: Disclosed herein is an arithmetic logic unit over a finite field GF(2m). Arithmetic logic units consistent with the present invention are disclosed as implemented using a division algorithm based on a binary greatest common divisor algorithm and a Most Significant Bit-first multiplication algorithm. The arithmetic logic unit can perform both a multiplication and a division using shared logic. Since the arithmetic logic unit has no limitations in the selection of an irreducible polynomial, and it is very regular and easily formed as a module, the arithmetic logic unit of the present invention has high expansibility and flexibility with respect to the size m of a field. Further, since the arithmetic logic unit of the present invention can perform a multiplication and a division using shared logic, it is very suitable to implement an encryption system for application products requiring a small size, such as smart cards or wireless communication devices.
Abstract: The present invention relates to a method and system for providing sine and cosine value pairs in a processor. The method includes decoding a sine and cosine instruction having a predetermined source angle and generating an index value for a sine cosine table (SCT) using a sine cosine control register (SCCR). The method also includes generating a plurality of quadrant bits using the SCCR, reading a sine and a cosine value pair from the SCT using the index value, and adjusting a sign of each value of the sine and the cosine value pair using the plurality of quadrant bits, if necessary. The method further includes incrementing the SCCR, if the SCCR is to be incremented, executing the sine and cosine instruction using the sine and cosine value pair, and outputting at least one result.
Abstract: A method and a circuit for masking digital data handled by an algorithm and factorized by a residue number system based on a finite base of numbers or polynomials prime to one another, comprising making the factorization base variable.
Abstract: An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.
Type:
Grant
Filed:
March 14, 2003
Date of Patent:
August 7, 2007
Assignee:
Matsushita Electric Industrial Co., Ltd.
Abstract: A method and apparatus for efficiently deriving modulo arithmetic solutions for frequency selection in transceivers. A frequency for communication between a wireless user interface device and a wirelessly enabled host is generated by calculating a modulo solution for an input variable. In some embodiments of the invention, the communication between the user input device and the wirelessly enabled host complies with the Bluetooth wireless communication standard. For the embodiments of the present invention relating to communications systems implementing the Bluetooth standard, a method and apparatus is disclosed for generating communication frequencies based on modulo 23 and modulo 79 solutions input variables. The method and apparatus of the present invention can generate the communication frequency with a minimum number of calculations using simple binary addition, as opposed to prior art methods that generally require numerous iterations and complex calculations.
Abstract: A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am?1tm?1+am?2tm?2+ . . . +a1t+a0, where the coefficients ai are equal to either 1 or 0, and m is a field degree. The reduction operation includes partially reducing a result of the arithmetic operation on the two binary polynomials to produce a congruent polynomial of degree less than a chosen integer n, with m?n. The partial reduction includes using a polynomial M?=(Mm(t)?tm)*tn?m, or a polynomial M?=Mm(t)*tn?m as part of reducing the result to the degree less than n and greater than or equal to m. The integer n can be the data path width of an arithmetic unit performing the arithmetic operation, a multiple of a digit size of a multiplier performing the arithmetic operation, a word size of a storage location, such as a register, or a maximum operand size of a functional unit in which the arithmetic operation is performed.