Abstract: An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate.

Abstract: A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The packgage allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate which has on at least one side thereof at least one integrated circuit device. Between adjacent subassemblies there is disposed a second substrate. There are electrical interconnection means to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies.

Abstract: Semiconductor chips are housed in respective cavities formed in a plate-like base substrate, and plate-like cap members are bonded onto the base substrate. The base substrate is diced to thereby form a plurality of semiconductor packages. Penetrating holes are formed in the base substrate between the cavities. The base substrate and the cap members are formed from alumina material of low purity or organic material. The hollow package structure prevents a deterioration in a high-frequency characteristic, and attains high productivity.

Abstract: The present invention relates to a fabrication method for integrated passive component, comprising the steps of providing an insulator substrate and then planarizing the insulator substrate; forming integrated passive components on the insulator substrate; and packaging the integrated passive components by a thick film packaging method. The advantages of the method of the invention are that the fabricated components are miniaturized, the yield is high, and cost of production is low.

Abstract: A microcap wafer-level package is provided in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer has gaskets formed thereon using a thick photoresist, semiconductor photolithographic process. Bonding pad gaskets match the perimeters of the bonding pads and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer. The cap wafer is then placed over the base wafer to cold weld bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket. The cap wafer is then thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for connecting wires from a micro device utilizing system.

Abstract: A mask 11 for vapor deposition is made of glass. Through-holes 15 are formed in the glass mask 11 so that they make a prescribed pattern on the surface of a semiconductor substrate 4. The peripheral wall of the through-hole is tapered so that the opening face 15b from which evaporated atoms are introduced is larger than the opening face 15a facing the deposition surface of the semiconductor substrate. The evaporated metal atoms having flied aslant toward the opening face 15b from which the evaporated atoms are introduced can pass through the through-hole 14 so that the evaporated metal atoms are deposited on the deposition surface of the semiconductor substrate. A desired thin film pattern inclusive of an electrode pattern can be easily formed on the surface of a semiconductor substrate, thereby improving the production yield of a semiconductor device.

Abstract: A connection component for a microelectronic device such as a semiconductor chip incorporates a support layer and conductive structures extending across a surface of the support layer. The conductive structures have anchors connecting them to the support layer, and releasable or unanchored portions. A method of making a connection component includes removing material from the conductive structures or the support layer or both to form the anchors.

Abstract: An interconnect for testing semiconductor wafers, and a method and system for testing wafers using the interconnect are provided. The interconnect includes a substrate with contact members configured to establish temporary electrical communication with contact locations (e.g., bond pads, test pads) on the wafer. For flat contact locations (e.g., thin film bond pads), the contact members comprise raised members with penetrating projections. For bumped contact locations (e.g., solder bumps), the contact members comprise indentations with a conductive layer. The interconnect also includes a pressure sensing mechanism for monitoring and controlling contact forces between the interconnect and wafer. In an illustrative embodiment the pressure sensing mechanism comprises a piezoresistive or piezoelectric layer and resistance measuring device.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a photoresist mask is patterned over the metal layer. The metal layer is etched and the portion of the metal layer not masked with the photoresist is removed. In this manner, additional metal can be formed on the pad site using only one additional mask step, and the thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments are processed using an auto-correlation function to produce an auto-correlation signal for each characteristic surface portion of the patterned feature. A reference signal having signal segments corresponding to characteristic surface portions of a known patterned feature is provided and each segment of the auto-correlation signal is compared to the respective signal segments of the reference signal.

Abstract: A process for producing a semiconductor substrate is provided which comprises a first step of anodizing a surface of a first substrate to form a porous layer on the surface, a second step of simultaneously forming a semiconductor layer on the surface of the porous layer and a semiconductor layer on a surface of the first substrate on its side opposite to the porous layer side, a third step of bonding the surface of the semiconductor layer formed on the surface of the porous layer to a surface of a second substrate, and a fourth step of separating the first substrate and the second substrate at the part of the porous layer to transfer to the second substrate the semiconductor layer formed on the surface of the porous layer, thereby providing the semiconductor layer on the surface of the second substrate. This makes it possible to produce semiconductor substrates at a low cost while making good use of expensive substrate materials.

Abstract: A switching device is described having a semiconductor substrate with a front side and a back side. The switching device includes a first transistor which includes a first region adjacent the front side, a second region within the first region, the semiconductor substrate, and at least one island region adjacent the backside. The switching device also includes a second transistor which includes the first region, the second region, the semiconductor substrate, and a third region coupled to the at least one island region.

Abstract: A method of controlling the resistance and improving the low temperature tolerance of a polysilicon resistor is provided. The method of the present invention employs a second annealing step after one of the high temperature (about 800° C. or above) device activation anneals. That is, the second annealing step can be used after source/drain activation, emitter activation or silicide formation. In accordance with the present invention, if a low temperature second annealing step below about 800° C. is performed after the high temperature device activation anneal, the resistance of the resistor increases, whereas when the second annealing temperature is higher than about 800° C., the resistance of the resistor decreases.

Abstract: To enable observation, analysis and evaluation of minute foreign substances by adopting a method for enabling performance of linkage between equipment coordinates of a particle examination equipment and apparatus coordinates of an analyzing apparatus such as SEM which is not a particle examination equipment with a precision higher than that with which coordinate linkage is performed between conventional equipment and apparatus coordinates. An analyzing method for analyzing minute foreign substances comprises the steps of determining the position of a minute foreign substance on the surface of a sample in a particle examination equipment, transferring the sample to a coordinate stage of an analyzing apparatus and inputting the position of the minute foreign substance determined by the particle examination equipment to thereby analyze the contents of this minute foreign substance.

Abstract: Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure.

Abstract: A semiconductor device includes a pair of semiconductor switching elements and a board. Each semiconductor switching element has positive and control electrodes formed on one surface and a negative electrode formed on the other surface. The positive and control electrodes of one of the semiconductor switching elements are joined to the board, and the negative electrode of the other semiconductor switching element, which faces in a direction opposite to that of one of the semiconductor switching elements, is joined to the board.

Abstract: A method of removing a polysilicon buffer in a method of forming a field oxide and an active area is disclosed herein that comprises the step of applying an etching selectivity solution to the polysilicon buffer to substantially remove the polysilicon buffer without substantially affecting the field oxide, a pad oxide, and the substrate. An etching selectivity solution is defined herein is a solution that has an etching rate for one material that is higher than for another material. In this case, the etching selectivity solution has an etching rate for polysilicon material that is higher than its etching rate for field oxide material. Accordingly, when the etching selectivity solution is applied to the polysilicon buffer, it will substantially etch off the polysilicon buffer without substantially affecting the field oxide. In the preferred embodiment, the etching selectivity solution comprises a mixture of HF and HNO3, or HF, HNO3 and CH3COOH.

Abstract: A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

Abstract: A passivating layer is provided for a III-V semiconductor. The passivating layer is preferably made of Fe and is used with III-V (especially GaAs) devices. At least one full monolayer of the passivating layer is formed, so that one full monolayer of the passivating layer bonds with one full monolayer of the atomic species of the semiconductor.