Abstract: An integrated circuit carrier comprising a modular substrate having an upper surface, a multitude of electrically conducting device terminals on the upper surface of the substrate, a multitude of electrically conducting engineering change pads also on the upper surface of the substrate, and an engineering change network to form a unique electrical connection between each of an arbitrary subset of the device terminals and each of an arbitrary subset of the engineering change pads. The engineering change network includes a multitude of connecting pads, and a multitude of first, second, and third conductive leads or wires, and each of the connecting pads includes first and second spaced apart sections.

Abstract: A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

Abstract: An electronic circuit apparatus in which electronic circuit components are mounted to multiwiring substrate or the like for use with electronic circuits such as an LSI are sealed airtight by sealing units. The sealing unit is sealed by an upper board designated as an upper board sealing unit and a side board designated as a side board sealing unit, and the shape of the edge on cross section of the side board is convex or circular. Metallization is applied to solder joint portions between a substrate and a side board and between the side board and the upper board, and a predetermined solder joint height is provided by a support post to effect solder joining.

Abstract: A semiconductor device is disclosed in which a long interaction path length is provided for a non-invasive probe beam. In a preferred embodiment, mirror surfaces are etched in the surface of the semiconductor substrate which are used to reflect the probe beam along the longest dimension of a charge carrier region of the semiconductor device. Interaction between the probe beam and the charge carriers present in the region is thereby enhanced.

Abstract: Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region.

Abstract: A semiconductor device includes a successively disposed a radiating electrode and hard radiating layer at the rear surface of a semiconductor wafer substrate which is divided into a plurality of semiconductor chips wherein the semiconductor chip includes the hard radiating layer having outer dimensions larger than that of substrate of said semiconductor chip.

Abstract: An infrared emitting semiconductor device having a layer-shaped infrared emitting region with a superlattice structure. The superlattice structure consists of thin alternating narrow and wide wells separated by thin barriers. The narrow well has one quasibound state E'.sub.0 while the wide well has two states E.sub.0 anad E.sub.1 with E'.sub.0 being located between E.sub.0 and E.sub.1. Under proper bias, an electron in state E.sub.0 can resonately tunnel out of the well through the quasibound state E'.sub.0 to the first excited state E.sub.1 of the next wide well. This electron can then relax to the ground state E.sub.0 where it can resonately tunnel to the next wide well and repeat the process. Infrared radiation with its photon energy equal to E.sub.1 -E.sub.0 is emitted as the electrons relax from E.sub.1 to E.sub.0 in the wide wells.

Abstract: A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film

Abstract: Provided is an integrated circuit device is used in an IC card or the like, and a manufacturing method of the integrated circuit device, having a thin thickness so as to be capable of being manufactured highly accurately in dimensions and highly efficiently. The integrated circuit element (12) is mounted on one surface of the thin metal plates (11) having the other surface which at least part serves as a plurality of external connecting terminals (11a) and, on one surface side, the integrated circuit element (12) is covererd with a sealing resin (15).

Abstract: Before spin-on-glass (SOG) is applied and soft-cured over metal traces (10) having a height/width aspect ratio (of the spaces) of at least 1, the aluminum metal traces are selectively coated with selective tungsten (16). After SOG (18) is spun on and soft-cured, it is etched back to expose the metal interconnects. A selective tungsten wet etch in H.sub.2 O.sub.2 detaches the SOG from the metal walls, leaving silt-like voids (20). Stress-free SOG hard curing may now proceed. A capping layer (22) of SOG may now be applied, soft-cured, then hard-cured. Alternatively, other dielectric materials may be applied as the capping layer. Further, interfacial lateral sidewall voids (24) may be deliberately left unfilled, by employing a capping layer (24') of vapor-deposited oxide. The unfilled voids have a dielectric constant of 1.0, which is useful in extremely high speed devices.

Abstract: A hermetically sealed chip carrier including a lead frame for use with an EEPROM chip, the carrier including a pre-molded plastic beam and an ultra violet transparent cover.

Abstract: A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film

Abstract: A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BICMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconencts.

Abstract: A semiconductor device includes a semiconductor pellet, and a metal nitride film or a metal silicide film, each having conductivity and an anti-oxidation property, and being formed on one surface of the pellet to cause the surface to have a substantially uniform potential.

Abstract: A semiconductor light-emitting device includes a pair of clad layers and an active layer sandwiched thereby which together are disposed between a substrate and a cap layer so as to form a monolithic array of double-heterojunction regions each including therein a plurality of light-emitting portions of the active layer for emitting light from the end face thereof so that the light-emitting portions are arrayed in a row and electrically separated from each other. The substrate is formed at one side thereof with a concave and convex configuration following a stripe pattern so that the clad layers, active layers and the cap layers are each arranged in the form of a corrugated configuration following the concave and convex configuration of the substrate.

Abstract: A circuit for reducing the latch-up sensitivity in complementary MOS technology includes a semiconductor substrate of a second conduction type. A first MOS transistor of a first complementary conduction type is disposed in the semiconductor substrate and has a source structure. A well of the first conduction type is disposed in the semiconductor substrate. A second MOS transistor of the second conduction type is disposed in the well and has a source structure. The semiconductor substrate and the source structure of the first transistor are connected to a first supply potential. The well and the source structure of the second transistor are connected to a second supply potential. A third transistor of the first conduction type is disposed in the semiconductor substrate between the first and second transistors. The third transistor has a gate connected to the first supply potential, a drain structure connected to the second supply potential, and a source structure connected to an output.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicated NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines having a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A semiconductor packaging technique employing a high Young's modulus, localized, external connection to pad, bond immobilizing member, together with, as needed, a low Young's modulus environmental protection covering member. A chip of Si or GaAs has an annulus of high Young's modulus epoxy over the line of external connections such as beam leads or wire bonds near the edge and a coating of silicone over the entire chip surface including the annulus.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: A packaged semiconductor device having heat transfer leads carrying a semiconductor chip directly or indirectly through a chip pad and extended to the exterior of the plastic or ceramics seal of the package, and a heat transfer cap held in surface contact with the extended heat transfer leads and covering upper side of the package. The heat generated in the semiconductor chip is transmitted to the upper side of the package and to the printed circuit board only through metallic parts so that the heat transfer is enhanced to remarkably reduce thermal resistance, thus enabling packaging of a semiconductor chip having a large heat generation rate.