Patents Examined by D. R. Hudspeth
  • Patent number: 4928022
    Abstract: Switching circuitry for automatically connecting two sets of terminals in two circuit modules, through a larger set of conductors, some of which may be defective or unavailable for other reasons. The circuitry includes two identical switching matrices, each of which receives signals indicative of the availability status of the conductors, and connects the terminals to an available subset of the conductors. Each switching matrix has an array of switching cells arranged in such a manner that a cell will connect a terminal to a conductor unless the conductor is not available, or unless the same terminal has already been assigned to another conductor, or the same conductor has already been assigned to another terminal.
    Type: Grant
    Filed: July 17, 1987
    Date of Patent: May 22, 1990
    Assignee: TRW Inc.
    Inventor: John R. Marum
  • Patent number: 4837460
    Abstract: The substrate voltages V.sub.1 and V.sub.2 of NMOS and PMOS transistors, respectively, which constitute a CMOS circuit and the source voltages V.sub.3 and V.sub.4 of these transistors have the following relationship:V.sub.1 <V.sub.3 <V.sub.4 <V.sub.2(where V.sub.1 may be equal to V.sub.3 or V.sub.4 may be equal to V.sub.2). In order to maintain the above relationship, it is preferable that internal power supply means are formed on the substrate upon which is also formed the CMOS circuit so that some of the above voltages may be produced.
    Type: Grant
    Filed: January 23, 1984
    Date of Patent: June 6, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukimasa Uchida
  • Patent number: 4798978
    Abstract: A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.
    Type: Grant
    Filed: April 30, 1987
    Date of Patent: January 17, 1989
    Assignee: Gain Electronics Corporation
    Inventors: Gary M. Lee, Charles M. Lee, George S. LaRue
  • Patent number: 4797575
    Abstract: A flip-flop circuit is provided for use in a phase-locked loop circuit, the flip-flop having two signal paths for selecting a VCO output during velocity lock and phase lock. The two signal paths comprise identical environments and therefore eliminate the phase step exhibited by prior art designs in shifting between velocity lock and phase lock. The circuit is also useful in any application where a clock to output delay of a flip-flop connected for normal operation, must have its propagation delay matched to a circuit which simply delays a signal by the same amount.
    Type: Grant
    Filed: December 5, 1986
    Date of Patent: January 10, 1989
    Assignee: Western Digital Corporation
    Inventor: Karl M. J. Lofgren
  • Patent number: 4795918
    Abstract: A temperature compensated bandgap voltage reference circuit employs an npn transistor based bypass circuit to maintain a constant collector current within the reference circuit. This bypass circuit draws a nominal current from the bandgap voltage reference circuit. The value of this current is set by a bias circuit responsive to changes in the supply voltage. As the supply voltage changes, the bias circuit varies the conductance of a bypass transistor to draw more or less current and thereby maintain the collector current within the reference circuit constant.
    Type: Grant
    Filed: May 1, 1987
    Date of Patent: January 3, 1989
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Suresh M. Menon, Jay L. Cohan
  • Patent number: 4794283
    Abstract: A logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals. An input amplifier having complementary devices is responsive to the differentiated signals to provide control signals to a feedback circuit which holds one of the devices in a conductive state and the other in a non-conductive state to provide an output signal having predetermined logic levels. Threshold voltage generating circuits biases each of the devices.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: December 27, 1988
    Assignee: Motorola, Inc.
    Inventors: Steven P. Allen, Robert C. Ledszius
  • Patent number: 4792706
    Abstract: The disclosure relates to a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Diode voltage ratios are very controllable since the diodes change only about 18 millivolts for every factor of two in current change. Thresholds can therefore easily be set in five and ten millivolt increments, this being the procedure utilized herein. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.
    Type: Grant
    Filed: December 16, 1986
    Date of Patent: December 20, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Kevin M. Ovens, Bobby D. Strong
  • Patent number: 4791320
    Abstract: A compound transistor type inverter, i.e., comprised of MIS and bipolar transistors, including, at the output stage thereof, an npn transistor operative to charge a load. The npn transistor can be quickly cut OFF by an additional transistor, and simultaneously, the additional transistor is operative to attain a quick discharge from the load. Still another additional transistor is employed, in a case where the inverter includes a pnp transistor, other than the npn transistor, at a ground side, which another additional transistor is operative to bypass the collector and emitter of the pnp transistor.
    Type: Grant
    Filed: August 18, 1986
    Date of Patent: December 13, 1988
    Assignee: Fujitsu Limited
    Inventors: Mitsuya Kawata, Tetsu Tanizawa
  • Patent number: 4791318
    Abstract: A circuit for controlling the circuit thresholds on an MOS integrated circuit takes advantage of the fact that all MOS devices of a particular type on the same chip have nearly identical characteristics. The circuit thresholds are varied by applying a control voltage to the back gate of an MOS device in each stage to be controlled. The control voltage is generated in a reference stage which utilizes a feedback loop to servo the back gate voltage of an MOS transistor in the loop. A reference voltage equal to the desired circuit threshold votlage is applied to the input of the reference stage. The reference voltage and the reference stage output are applied to an amplifier in the feedback loop. The amplifier applies to the back gate of the MOS transistor in the reference stage a control voltage that tends to equalize or establish a desired offset between the reference voltage and the reference stage output.
    Type: Grant
    Filed: December 15, 1987
    Date of Patent: December 13, 1988
    Assignee: Analog Devices, Inc.
    Inventors: Stephen R. Lewis, Scott Lefton
  • Patent number: 4791319
    Abstract: A semiconductor device such as a DRAM with many signal line circuits is also provided with a redundancy circuit and is so structured that when one of the signal line circuits is defective and the fuse contained by such a defective signal line circuit is cut off to inactivate it, an input signal which would select the inactivated signal line circuit will automatically select the redundancy circuit.
    Type: Grant
    Filed: April 29, 1987
    Date of Patent: December 13, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoyuki Tagami, Masaru Nawaki
  • Patent number: 4791317
    Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit connects a capacitor bias generator to the capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit disconnects the capacitive bias generator from the capacitor when a voltage on the substrate bias terminal is greater than the sum.
    Type: Grant
    Filed: March 13, 1987
    Date of Patent: December 13, 1988
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef Winnerl, Werner Reczek
  • Patent number: 4791316
    Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit disconnects a capacitor bias generator from the capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and a threshold voltage of a first transistor in the electronic protection circuit.
    Type: Grant
    Filed: March 13, 1987
    Date of Patent: December 13, 1988
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef Winnerl, Werner Reczek, Wolfgang Pribyl
  • Patent number: 4789797
    Abstract: An interface circuit (110) for interfacing between an "OR-tied" connection (P) of a programmable logic array device (10) and a TTL output buffer (36) includes a first bandgap generator (40), a high level clamp circuit (30), a second bandgap generator circuit (42), and a sensing circuit (26). The first bandgap generator (40) generates a first reference voltage (VB1) which has a positive temperature coefficient. The second bandgap generator (42) generates a second reference voltage (VB2) which has a negative temperature coefficient. A resultant base drive current (I.sub.x) is supplied to the base of a phase splitter transistor (Q2) in the output buffer (36). The resultant current (I.sub.x) is controlled by the first and second bandgap generators (40, 42), the current being higher at low temperatures and being smaller at high temperatures.
    Type: Grant
    Filed: June 25, 1987
    Date of Patent: December 6, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nader Vasseghi
  • Patent number: 4788457
    Abstract: A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line.
    Type: Grant
    Filed: September 9, 1987
    Date of Patent: November 29, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koichiro Mashiko, Kazutami Arimoto, Kiyohiro Furutani, Noriaki Matsumoto, Yoshio Matsuda
  • Patent number: 4788455
    Abstract: An internal power supply voltage generator for generating an internal power supply voltage for a semiconductor integrated device includes first and second reference voltage generators which produce first and second reference voltages having respective values a predetermined amount above and below an optimal value of the internal power supply voltage. The first and second reference voltage generators are constructed of a pair of serially connected NMOS and PMOS transistors, respectively, which transistors are connected between an external voltage supply and ground. The first and second reference voltages are applied to a CMOS output stage constructed of a NMOS and PMOS transistor serially connected between the external voltage supply and ground, the gates of the transistors being coupled to the first and second reference voltages, so as to provide said internal power supply voltage at a common node between the transistors.
    Type: Grant
    Filed: August 1, 1986
    Date of Patent: November 29, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Mori, Hiroshi Miyamoto, Tadato Yamagata, Michihiro Yamada, Kazutami Arimoto
  • Patent number: 4788460
    Abstract: For improvement of operation speed, a sense amplifier circuit comprising (a) a signal input node, (b) a signal output node, (c) load means with a relatively large resistance provided between a source of voltage and the signal output node, (d) a first field effect transistor with a relatively small channel resistance provided between the signal input node and the signal output node and having a gate electrode, (e) a logic gate having at least one input node connected to the signal input node and an output node connected to the gate electrode of the first field effect transistor, and (f) a second field effect transistor with a relatively small channel resistance provided between the source of voltage and the signal output node and having a gate electrode connected to the output node of the logic gate.
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: November 29, 1988
    Assignee: NEC Corporation
    Inventor: Hiroyuki Kobatake
  • Patent number: 4786830
    Abstract: A TTL to CMOS-input buffer has minimal sensitivity of threshold level variation with changes in device parameters. In particular, the design is insensitive to P-channel characteristics over very wide ranges of transistor threshold voltages and gain parameter spreads.
    Type: Grant
    Filed: June 22, 1987
    Date of Patent: November 22, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Richard C. Foss
  • Patent number: 4786829
    Abstract: Disclosed herein is a simple latched-fedback-memory finite-state-engine that produces an inherently stable output upon the receipt of a clock signal, that is synchronously or asynchronously generated. The finite-state-engine comprises at least three latches and a function module, wherein the output of one latch is used as an input for the function module and a previous output of the function module is re-entered as an input into the function module.
    Type: Grant
    Filed: February 24, 1987
    Date of Patent: November 22, 1988
    Inventor: John H. Letcher
  • Patent number: 4785202
    Abstract: A semiconductor integrated circuit device according to the present invention comprising an electric circuit formed in a semiconductor substrate, said circuit including first and second nodes between which a potential difference is provided, a wiring of a large ground capacitance connected to the first node, and a bypass capacitor connected to the second node, said wiring and bypass capacitor being of an integral structure prepared by laminating an upper conductor film pattern connected to the second node via an insulating film on a lower conductor film pattern connected to the first node. A MIM-structure in which a wiring and a bypass capacitor are made integral is employed in the semiconductor integrated circuit device of the present invention, making it possible to eliminate the large area required for forming the independent bypass capacitor. Also, the ratio of the ground capacitance of the wiring to the capacitance of the bypass capacitor is constant regardless of the change in the length of the wiring.
    Type: Grant
    Filed: April 6, 1987
    Date of Patent: November 15, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuyuki Toyoda
  • Patent number: 4785207
    Abstract: A leakage regulator for use with switching power supplies which include a field effect transistor (FET) is disclosed. The leakage regulator comprises a bias circuit coupled in a feedback arrangement with the FET to provide a self-generated bias voltage. The bias circuit includes a current transformer coupled to receive a drain-source leakage current. A bias voltage is generated from the transformed leakage current and this bias voltage is applied to the FET gate to help decrease the leakage current.
    Type: Grant
    Filed: January 21, 1987
    Date of Patent: November 15, 1988
    Assignee: Hughes Aircraft Company
    Inventor: John E. Eng