Patents Examined by Daniel P Shook
  • Patent number: 10707347
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Patent number: 10707300
    Abstract: A semiconductor device having a trench gate structure is provided. A semiconductor device is provided, including: a first-conductivity-type drift region provided in a semiconductor substrate; a first-conductivity-type accumulation region provided above the drift region and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region; and an electric-field relaxation layer provided between the accumulation region and the base region and having a lower doping concentration than the accumulation region. The electric-field relaxation layer may include a first-conductivity-type region including a region having a same doping concentration as the drift region.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: July 7, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yosuke Sakurai, Yuichi Onozawa, Akio Nakagawa
  • Patent number: 10700124
    Abstract: A spin-orbit torque magnetoresistive random access memory, and a method for manufacturing a spin-orbit torque magnetoresistive random access memory are provided. The spin-orbit torque magnetoresistive random access memory includes a spin-orbit coupling layer and a magnetoresistive tunnel junction located on the spin-orbit coupling layer. The magnetoresistive tunnel junction includes a first magnetic layer, a tunneling layer, and a second magnetic layer that are sequentially stacked from bottom to top, and each of the first magnetic layer and the second magnetic layer has perpendicular anisotropy. In a direction of a current in the spin-orbit coupling layer, defects are generated in a part of the magnetoresistive tunnel junction by an ion implantation process.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 30, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Meiyin Yang, Jun Luo, Tengzhi Yang, Jing Xu
  • Patent number: 10692758
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 23, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Chich-Neng Chang
  • Patent number: 10692723
    Abstract: A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shuo Hsieh, Shih-Chang Tsai, Chih-Han Lin, Te-Yung Liu
  • Patent number: 10685963
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiseok Lee, Keunnam Kim, Eun A Kim, Eunjung Kim, Jeongseop Shim
  • Patent number: 10680016
    Abstract: The disclosure provides a flexible display panel, a method for fabricating the same, and a flexible display device. A flexible display panel according to an embodiment of the disclosure includes at least one bendable area; a neutral layer adjusting structure arranged in the at least one bendable area, and configured to adjust the position of a neutral layer in the bendable area where the neutral layer adjusting structure is located; and a flexible element located in the bendable area, and configured to be approximately located at the neutral layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 9, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tao Wang, Weifeng Zhou
  • Patent number: 10672837
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer including a p-type semiconductor and an n-type semiconductor, and provided between the first electrode and the second electrode, in which the photoelectric conversion layer has an exciton charge separation rate of 1×1010 s?1 to 1×1016 s?1 both inclusive in a p-n junction surface formed by the p-type semiconductor and the n-type semiconductor.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: June 2, 2020
    Assignee: SONY CORPORATION
    Inventors: Hajime Kobayashi, Yuichi Tokita
  • Patent number: 10665682
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer provided between the silicon carbide layer and the gate electrode; and a region located between the silicon carbide layer and the gate insulating layer, the region having a first bonding structure, the first bonding structure including a threefold coordinated first nitrogen atom bonded to three first silicon atoms, a threefold coordinated second nitrogen atom bonded to three second silicon atoms, and a threefold coordinated third nitrogen atom bonded to three third silicon atoms, the first to third nitrogen atoms being adjacent to each other in the first bonding structure.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 26, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10665580
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Kazuma Shimamoto, Tetsuya Shirasu, Yuji Fukano, Akio Nishida
  • Patent number: 10665458
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 26, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer
  • Patent number: 10665546
    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 26, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Da-jun Lin, Bin-Siang Tsai, San-Fu Lin
  • Patent number: 10658448
    Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG CO., LTD.
    Inventors: Jun Won Choi, Dong Soo Kim, Hyun-Chol Bang, Chang Soo Pyon, Ji-Eun Lee
  • Patent number: 10644053
    Abstract: A substrate includes a plurality of pixels arranged in a two-dimensional array structure and has a front side and a back side opposite to the front side. An interconnection is arranged on the front side of the substrate. An insulating layer, a color filter, and a micro-lens are arranged on the back side of the substrate. A pixel separation structure is disposed in the substrate. The pixel separation structure includes a conductive layer having a grid structure in a planar view of the image sensor and surrounds each of the plurality of pixels. A back side contact is vertically overlapped with and electrically connected to a grid point portion of the grid structure of the conductive layer of the pixel separation structure.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-seok Kim, Byung-jun Park, Hee-geun Jeong, Seung-joo Nah
  • Patent number: 10636842
    Abstract: A method for forming a resistive random access memory includes forming a layer stack, patterning the layer stack to form a plurality of stack structures, forming a protection layer along sidewalls of the plurality of stack structures, forming a first isolation structure between the plurality of stack structures, forming at least one recess in at least one stack structure to define a plurality of filament units, and forming a second isolation structure in the at least one recess. The layer stack includes a bottom electrode and a resistive switching layer on the bottom electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 28, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chia-Wen Cheng, Yi-Hsiu Chen, Po-Yen Hsu, Ping-Kun Wang, Ming-Che Lin, He-Hsuan Chao
  • Patent number: 10622331
    Abstract: One aspect relates to a method for manufacturing a substrate assembly for attachment to an electronic component A substrate is provided with a first side and a second side. A contact material layer is applied to the first side of the substrate. A pre-fixing agent is applied at least to sections of a side of the contact material layer facing away from the substrate.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 14, 2020
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Andreas Hinrich, Susanne Duch, Anton Miric, Michael Schäfer, Christian Bachmann, Holger Ulrich, Frank Osterwald, David Benning, Jacek Rudzki, Lars Paulsen, Frank Schefuss, Martin Becker
  • Patent number: 10622333
    Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 14, 2020
    Assignee: Intel IP Corporation
    Inventor: Richard Patten
  • Patent number: 10615291
    Abstract: The semiconductor substrate may include an emitter region, an upper body region being in direct contact with the gate insulating film below the emitter region, an intermediate region being in direct contact with the gate insulating film below the upper body region, a lower body region being in direct contact with the gate insulating film below the intermediate region, a drift region being in direct contact with the gate insulating film below the lower body region, and a collector region being in direct contact with the drift region from below. The lower body region may include a first range and a second range that has a higher crystal defect density than the first range. The second range may be in direct contact with the gate insulating film. The first range may be in direct contact with the second range on a side opposed to the gate insulating film.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 7, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Keisuke Kimura
  • Patent number: 10615231
    Abstract: An organic light emitting diode substrate, a method for manufacturing an organic light emitting diode substrate, and a display panel. The organic light emitting diode substrate includes: a base substrate; a pixel defining layer on the base substrate; and an anode, an organic light emitting diode functional layer and a cathode in a pixel region. The pixel defining layer includes a first pixel defining layer, an auxiliary cathode and a second pixel defining layer sequentially stacked, the auxiliary cathode being connected to the cathode.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: April 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Haidong Wu, Yansong Li, Xiaobo Du
  • Patent number: 10608001
    Abstract: A nonvolatile memory device includes a plurality of unit cells. Each of the plurality of unit cells includes a first active region disposed in a substrate to extend in a first direction, a floating gate extending in a second direction to cross over the first active region, a first selection gate disposed to be adjacent to a first side surface of the floating gate to cross over the first active region, a second selection gate disposed to be adjacent to a second side surface of the floating gate opposite to the first selection gate to cross over the first active region, a first dielectric layer disposed between the floating gate and the first selection gate, and a second dielectric layer disposed between the floating gate and the second selection gate.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix system ic Inc.
    Inventor: Kwang Il Choi