Abstract: A method of producing a light transmissive element includes providing a holding member including an upper surface and a plurality of holes, each of the plurality of holes having at least one inner lateral surface that is a substantially smooth surface and an opening in the upper surface of the holding member; filling the plurality of holes with a wavelength conversion member containing fluorescent particles and a light transmissive member such that the wavelength conversion member is in contact with the inner lateral surface of each of the plurality of holes; molding the wavelength conversion member; and taking out the wavelength conversion member from the holding member after the molding of the wavelength conversion member.

Abstract: An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor device manufacturing method, sequentially includes a semiconductor element preparation step of preparing a first semiconductor element on which is formed a plurality of metal electrodes, a step of covering a surface of the first semiconductor element on which the metal electrode is not formed with a first insulating member, and a step of forming a second metal layer that conductively connects the metal electrode of the first semiconductor element and a first metal layer on an insulated circuit substrate across the second insulating member.

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

Abstract: An imaging device including a unit pixel cell including a semiconductor substrate having a surface including a first area and a second area surrounded by the first area. The semiconductor substrate including a first region of a first conductivity type exposed to the surface in the first area, and a second region of a second conductivity type directly adjacent to the first region and exposed to the surface in the second area; a photoelectric converter; an amplifier; a contact plug connected to the second region; a first transistor including a first electrode; a second electrode covering a second portion of the first area; and a second insulation layer between the second electrode and the semiconductor substrate. When viewed in a direction perpendicular to the surface of the semiconductor substrate, a contact between the second region and the contact plug is located between the first electrode and the second electrode.

Abstract: A first substrate includes a plurality of unit pixel regions. A deep trench isolation structure is disposed in the first substrate and isolates each of the plurality of the unit pixel regions from each other. Each of a plurality of photoelectric converters is disposed in one of the plurality of unit pixel regions. A plurality of micro lenses are disposed on the first substrate. A plurality of light splitters are disposed on the first substrate. Each of the plurality of light splitters is disposed between one of the plurality of micro lenses and one of the plurality of photoelectric converters. Each of a plurality of photoelectric-conversion-enhancing layers is disposed between one of the plurality of light splitters and one of the plurality of photoelectric converters.

Abstract: A shared floating gate device, the device including an nFET including an nFET gate dielectric, a pFET including a pFET gate dielectric, and a floating gate, where the nFET and the pFET are connected in parallel and share the floating gate.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

Abstract: Disclosed are a semiconductor structure of an ESD protection device with low capacitance and a method for manufacturing the same. The method for manufacturing a semiconductor structure of an ESD protection device, comprising: forming a buried layer with a first doping type and a buried layer with a second doping type in a first region and a second region at a top surface of a semiconductor substrate with a first doping type, respectively; forming an epitaxial layer with a second doping type on the buried layer with the first doping type and the buried layer with the second doping type, wherein the buried layer with the first doping type and the buried layer with the second doping type are buried between the semiconductor substrate and the epitaxial layer, a first doped region with a first doping type is formed at a top of a third region on the buried layer with the second doping type located on the epitaxial layer.

Abstract: A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure.

Abstract: Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

Abstract: An optoelectronic component is disclosed. In an embodiment the optoelectronic component includes an active zone configured to produce electromagnetic radiation, wherein the active zone has at least two quantum films, wherein the first quantum film is arranged between a first barrier layer and a second barrier layer, wherein the second quantum film is arranged between the second barrier layer and a last barrier layer, and wherein bandgaps of the first barrier layer and of the second barrier layer are related differently to one another than bandgaps of the second barrier layer and of the last barrier layer.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

Abstract: A flexible display panel and a flexible display apparatus are provided. The flexible display panel comprises a flexible substrate, an organic light-emitting layer disposed on a side of the flexible substrate and having a first side facing the flexible substrate and an opposing side, and a thin-film-encapsulation layer disposed on the opposing side of the organic light-emitting layer and including at least one organic encapsulation layer and at least one inorganic encapsulation layer. The flexible display panel includes at least one bending area. The at least one organic encapsulation layer has a first side facing the flexible substrate and an opposing side. In the at least one bending area, at least one groove is formed on the opposing side of the at least one organic encapsulation layer. A bottom width W of the at least one groove is configured to be W ? n 180 ? ° ? ? ? ? R .

Abstract: Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs.

Abstract: A method of forming an electronic field emission rectifier involves depositing a first metal layer, a dielectric, and a second metal layer on a substrate in that order. The dielectric layer and the second metal layer are patterned. Patterning the dielectric and second metal layers involves depositing a nanostructuring layer on the second metal layer. The nanostructuring layer self-assembles into removable regions embedded within a matrix. When the removable regions are removed, a pattern is formed in the matrix.

Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Abstract: A semiconductor device includes: an n? type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench formed in the n? type layer and separated from each other; an n+ type region disposed between a side surface of the first trench and the side surface of the second trench and disposed on the n? type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer, the n+ type region, and the source insulating layer; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.