Patents Examined by Dao H. Nguyen
  • Patent number: 11508738
    Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin
  • Patent number: 11508655
    Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Shun Chang, Meng-Wei Hsieh, Teck-Chong Lee
  • Patent number: 11508736
    Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11508768
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving sensitivity while suppressing deterioration of color mixing. The solid-state imaging device includes a substrate, a first photoelectric conversion region in the substrate, a second photoelectric conversion region in the substrate, a trench between the first photoelectric conversion region and the second photoelectric conversion region and penetrates through the substrate, a first concave portion region that has a plurality of concave portions provided on a light receiving surface side of the substrate, above the first photoelectric conversion regions, and a second concave portion region that has a plurality of concave portions provided on the light receiving surface side of the substrate, above the second photoelectric conversion region. The technology of the present disclosure can be applied to, for example, a backside illumination solid-state imaging device and the like.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 22, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Itaru Oshiyama
  • Patent number: 11502122
    Abstract: The present technology relates to an imaging element and an electronic device enabling suppression of generation of noise. Provided with a substrate, a first photoelectric conversion region provided on the substrate, a second photoelectric conversion region provided on the substrate and adjacent to the first photoelectric conversion region, a trench provided on the substrate and between the first photoelectric conversion region and the second photoelectric conversion region, a first impurity region including a first impurity provided on the substrate and on a sidewall of the trench, and a second impurity region including a second impurity provided on the substrate and between the first photoelectric conversion region or the second photoelectric conversion region and the first impurity region. The present technology can be applied to an imaging element.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 15, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Haruyuki Nakagawa
  • Patent number: 11502121
    Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Min-Feng Kao, Jen-Cheng Liu, Feng-Chi Hung, Dun-Nian Yaung
  • Patent number: 11502109
    Abstract: A highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate. The capacitor includes a region where the first electrode and the dielectric film are in contact with each other, and the first insulating film does not cover the region.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: November 15, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 11482557
    Abstract: Provided are a solid-state image-capturing device, a semiconductor apparatus, an electronic apparatus, and a manufacturing method that enable improvement in reliability of through electrodes and increase in density of through electrodes. A common opening portion is formed including a through electrode formation region that is a region in which the plurality of through electrodes electrically connected respectively to a plurality of electrode pads provided on a joint surface side from a device formation surface of a semiconductor substrate is formed. A plurality of through portions is formed so as to penetrate to the plurality of respective electrode pads in the common opening portion, and wiring is formed along the common opening portion and the through portions from the electrode pads to the device formation surface corresponding to the respective through electrodes. The present technology can be applied to a layer-type solid-state image-capturing device, for example.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 25, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoichi Ootsuka
  • Patent number: 11482602
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 25, 2022
    Inventors: Hyun-Seung Song, Tae-Yeol Kim, Jae-Jik Baek
  • Patent number: 11482592
    Abstract: A substrate, a manufacturing method of a substrate and an electronic device are provided. The substrate includes a working region, a non-working region surrounding the working region, a base substrate, a peripheral circuit and a common electrode lead both in the non-working region and on the substrate; the common electrode lead is located on a side of the peripheral circuit close to the working region.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 25, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Minho Ko, Wanli Dong
  • Patent number: 11476333
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen
  • Patent number: 11462512
    Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kamal K. Sikka, Fee Li Lie, Kevin Winstel, Ravi K. Bonam, Iqbal Rashid Saraf, Dario Goldfarb, Daniel Corliss, Dinesh Gupta
  • Patent number: 11456253
    Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between the main circuit region and the scribe region.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
  • Patent number: 11456357
    Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 27, 2022
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Anupama Bowonder, William Hsu, Szuya S. Liao, Mehmet Onur Baykan, Tahir Ghani
  • Patent number: 11444124
    Abstract: A resistive random-access memory (ReRAM) includes a hybrid memory cell. The hybrid memory cell includes: (a) a left resistance-switching device comprising a first terminal and a second terminal, (b) a right resistance-switching device comprising a first terminal and a second terminal, wherein the first terminal of the right resistance-switching device is connected to the first terminal of the left-resistive switching device at an internal node, and (c) a transistor comprising a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the transistor is connected to the left resistance-switching device and the right resistance-switching device at the internal node.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 13, 2022
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Kwang Ting Cheng, Miguel Angel Lastras MontaƱo
  • Patent number: 11444017
    Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 13, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
  • Patent number: 11444005
    Abstract: The present technology relates to a semiconductor device, an imaging device, and a manufacturing apparatus, capable of providing a semiconductor substrate maintaining and improving insulating performance. A through hole that penetrates the semiconductor substrate, an electrode at the center of the through hole, and a space around the electrode are included. The through hole also penetrates an insulating film formed on the semiconductor substrate. A barrier metal is further included around the electrode. An insulating film is further included in the semiconductor substrate and the space. The semiconductor device has a multilayer structure, and the electrode connects wirings formed in different layers to each other. The present technology can be applied to, for example, an image sensor in which a logic circuit and a sensor circuit are laminated.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 13, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Reijiroh Shohji
  • Patent number: 11437316
    Abstract: A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard T. Schultz, John J. Wuu
  • Patent number: 11437292
    Abstract: A sensing module, a semiconductor device package and a method of manufacturing the same are provided. The sensing module includes a sensing device, a first protection film and a second protection film. The sensing device has an active surface and a sensing region disposed adjacent to the active surface of the sensing device. The first protection film is disposed on the active surface of the sensing device and fully covers the sensing region. The second protection film is in contact with the first protection film and the active surface of the sensing device.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 6, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Wei Liu, Huei-Siang Wong, Lu-Ming Lai
  • Patent number: 11437495
    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chih Chen, Ru-Shang Hsiao, Ching-Pin Lin, Chih-Mu Huang, Fu-Tsun Tsai