Patents Examined by Dao H. Nguyen
  • Patent number: 10808171
    Abstract: An infrared emitting fluoride phosphor and an infrared light emitting device are provided. The infrared emitting fluoride phosphor includes an activation center of Cr3+. The infrared light emitting device includes a light source and the infrared emitting fluoride phosphor. The light source is disposed to emit a first light, and the first light has a wavelength of 400-700 nm. The infrared emitting fluoride phosphor is configured to be excited by the first light to emit a first infrared ray. The first infrared ray has a wavelength of 650-1000 nm. The infrared light emitting device has a broad emission wavelength, such that it can be applied in variety of sensing device.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 20, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chi Lee, Mu-Huai Fang, Ru-Shi Liu, Yi-Ting Tsai, Tzong-Liang Tsai, Yu-Chun Lee
  • Patent number: 10811298
    Abstract: An apparatus is provided, comprising: a wafer having a first planar surface and a second surface opposite the first surface. The second surface includes a plurality of recesses. Each recess includes a plurality of sidewalls and a lower surface and is configured to receive a semiconductor device. The plurality of sidewalls of each recess is configured to align the semiconductor device and constrain the semiconductor device from moving in a direction parallel to the second surface.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jing Cheng Lin
  • Patent number: 10804166
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 10804289
    Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Vit Yang, Yong Hoon Son, Moon Jong Kang, Hyuk Ho Kwon, Sung Soo Ahn, So Yoon Lee
  • Patent number: 10804307
    Abstract: Some aspects of the present disclosure relate to a method. In the method, a semiconductor substrate is received. A photodetector is formed in the semiconductor substrate. An interconnect structure is formed over the photodetector and over a frontside of the semiconductor substrate. A backside of the semiconductor substrate is thinned, the backside being furthest from the interconnect structure. A ring-shaped structure is formed so as to extend into the thinned backside of the semiconductor substrate to laterally surround the photodetector. A series of trench structures are formed to extend into the thinned backside of the semiconductor substrate. The series of trench structures are laterally surrounded by the ring-shaped structure and extend into the photodetector.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 10804219
    Abstract: A semiconductor device includes a plurality of lower electrodes repeatedly arranged at a first pitch in a first direction and a second direction crossing the first direction at an acute angle on a substrate, and a support pattern in contact with sidewalls of the plurality of lower electrodes and supporting the plurality of lower electrodes. The support pattern includes a first support region having a plurality of openings penetrating the support pattern and a second support region disposed at a periphery of the first support region. The plurality of openings may continuously extend in a zigzag manner, respectively, throughout an entirety of the first support region.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Wan Gi Sohn
  • Patent number: 10796999
    Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Boon Ping Koh, Eng Huat Goh, Jiun Hann Sir, Khang Choong Yong, Min Suet Lim, Wil Choon Song
  • Patent number: 10790441
    Abstract: A switching device, comprising an anti-ferromagnet structure having an upper layer and a lower layer, the upper layer and lower layer anti-ferromagnetically coupled by an exchange coupling layer, the upper and lower layer formed of a similar material but having differing volumes, and wherein the device is configured to inject symmetrically spin-polarized currents through the upper and lower layers to achieve magnetic switching of the anti-ferromagnet structure.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 29, 2020
    Assignee: Purdue Research Foundation
    Inventors: Kerem Y. Camsari, Ahmed Zeeshan Pervaiz, Rafatul Faria, Esteban E Marinero-Caceres, Supriyo Datta
  • Patent number: 10784202
    Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier
  • Patent number: 10784376
    Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Hwan Kim, Gigwan Park, Junggun You, DongSuk Shin, Jin-Wook Kim
  • Patent number: 10777639
    Abstract: Disclosed are a two-dimensional semiconductor in which an energy band gap changes with thickness, a manufacturing method therefor, and a semiconductor device comprising the same. A two-dimensional semiconductor according to an embodiment comprises: a first layer having a first thickness; and a second layer having a second thickness, wherein the first thickness and the second thickness are different from each other, the first layer forms a first junction with a first electrode, and the second layer forms a second junction with a second electrode.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: September 15, 2020
    Assignees: KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP, Korea Advanced Institute of Science and Technology
    Inventors: Hyun Jong Chung, Hyun Cheol Kim, Han Byeol Lee, Hak Seong Kim, Sung Yool Choi
  • Patent number: 10777590
    Abstract: A method for forming an image sensor device structure is provided. The method includes forming a light-sensing region in a substrate, and forming an interconnect structure below a first surface of the substrate. The method also includes forming a trench in the light-sensing region from a second surface of the substrate, and forming a doping layer in the trench. The method includes forming an oxide layer in the trench and on the doping layer to form a doping region, and the doping region is inserted into the light-sensing region.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Yu-Jen Wang, Shyh-Fann Ting, Wei-Chuang Wu, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10777428
    Abstract: Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 15, 2020
    Assignee: INTEL CORPORATION
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli
  • Patent number: 10770377
    Abstract: A leadframe includes a die pad for mounting a semiconductor die with its top side facing up using a die attach resin material including a resin, the leadframe having leads or lead terminals beyond the die pad. The die pad includes slots including a first slot and at least a second slot on at least a first side of the die pad that penetrate a full thickness of the die pad. At least one non-penetrating groove is in the die pad for providing a fluid connection including between the first and second slots for providing a flow channel for guiding the resin when received by the grooves after bleeding out from under the semiconductor die to flow to at least one of the first slot and the second slot.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joel De Guzman Raposas, Rolando Mendoza Chan, Kent Lacson Capan
  • Patent number: 10770398
    Abstract: A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 10770571
    Abstract: A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hao Hsu, Yu-Chun Ko, Yu-Chang Liang, Kao-Ting Lai
  • Patent number: 10763186
    Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Wayne H. Huang, Owen R. Fay
  • Patent number: 10763224
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10756264
    Abstract: The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 25, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Frederick Chen
  • Patent number: 10756184
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Timothy J. McArdle, Judson R. Holt, Steffen A. Sichler, Ömür I. Aydin, Wei Hong, Yi Qi, Hui Zang, Liu Jiang