Patents Examined by Dao H. Nguyen
  • Patent number: 10411131
    Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Hwan Kim, Gigwan Park, Junggun You, DongSuk Shin, Jin-Wook Kim
  • Patent number: 10411141
    Abstract: A semiconductor device includes: a semiconductor base body where a second semiconductor layer is stacked on a first semiconductor layer, a trench is formed on a surface of the second semiconductor layer, and a third semiconductor layer which is formed of an epitaxial layer is formed in the inside of the trench; a first electrode; an interlayer insulation film which has a predetermined opening; and a second electrode, wherein metal is filled in the opening, the opening is disposed at a position avoiding a center portion of the third semiconductor layer, the second electrode is connected to the third semiconductor layer through the metal, and a surface of the center portion of the third semiconductor layer is covered by the interlayer insulation film.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 10, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki, Daisuke Arai
  • Patent number: 10405433
    Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 3, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10403593
    Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: September 3, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Takeshi Suzuki, Masashi Yamaura
  • Patent number: 10381317
    Abstract: The present invention relates to a transition arrangement (100) comprising a transition between a substrate integrated waveguide, SIW, (20) of a circuit arrangement and a waveguide and/or antenna structure (10). It comprises a first conducting plate (1) and a second conducting plate (2). The SIW (20) is arranged on said first conducting plate, and an impedance matching structure (4) is connected to the second conducting plate.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 13, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Rob Maaskant, Alhassan Aljarosha, Ashraf Uz Zaman
  • Patent number: 10377627
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: August 13, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Merrill Albert Hatcher, Jr., Jonathan Hale Hammond, Jon Chadwick, Julio C. Costa, Jan Edward Vandemeer
  • Patent number: 10381355
    Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Kangguo Cheng, Zhenxing Bi, Juntao Li
  • Patent number: 10366838
    Abstract: A laminated ceramic electronic component that includes a laminate having a plurality of dielectric layers and a plurality of internal electrode layers laminated together. External electrodes having underlying electrode layers and plating layers are formed on both end surfaces of the laminate. When a cross-section including the underlying electrode layers is observed, the underlying electrode layers contain a plurality of Cu crystals and glass, and an average value of lengths of demarcation lines of the Cu crystals having different crystal orientations is 3 ?m or less.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Masato Kimura
  • Patent number: 10367009
    Abstract: Provided is an active-matrix substrate in which the line resistance is decreased. The active-matrix substrate includes a substrate 31, a plurality of gate lines Gj disposed on the substrate 31 and extending in a first direction, a plurality of source lines Si disposed on the substrate 31 and extending in a second direction different from the first direction, a transistor 2 disposed correspondingly to each of intersection points of the gate lines and the source lines Si and connected to a corresponding one of the gate lines Gj and a corresponding one of the source lines Si, an insulating layer, and extended conductive films 51, 52, and 61. At least ones of the gate lines Gj and the source lines Si each have a layered structure with connection to the extended conductive film via a contact hole provided in the insulating layer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: July 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Fumiki Nakano
  • Patent number: 10366843
    Abstract: A structural capacitor and method for manufacturing the structural capacitor. A first layer of nonconductive fiber glass may be formed into a desired shape of the structural capacitor, and then a conductive layer made of carbon fiber pre-impregnated material may be placed on the fiber glass layer. A dielectric layer of parylene may then be coated onto the conductive layer using a conformal vapor deposition process. More conductive and dielectric layers may be added in alternating succession until desired structural and/or electrical properties are achieved. A final layer of fiber glass may then be applied and the resulting structural capacitor may be cured.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 30, 2019
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Steven Todd LaPlant, Daniel John Salzman
  • Patent number: 10361237
    Abstract: Light sensors and methods of making the same include a photodiode and a hole accumulation layer directly on a sensing surface of the photodiode. A metal oxide layer is formed over the hole accumulation layer. An anti-reflection layer is formed over the metal oxide layer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee
  • Patent number: 10355102
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 10355144
    Abstract: A heat-dissipating Zener diode includes a heavily-doped semiconductor substrate having a first conductivity type, a first epitaxial layer having the first conductivity type, a first heavily-doped area having a second conductivity type, a second epitaxial layer, and a second heavily-doped area having the second conductivity type or the first conductivity type. The first epitaxial layer is formed on the heavily-doped semiconductor substrate. The first heavily-doped area is formed in the first epitaxial layer and spaced from the heavily-doped semiconductor substrate. The second epitaxial layer is formed on the first epitaxial layer and penetrated with a first doped area, and the first doped area has the second conductivity type and contacts the first heavily-doped area. The second heavily-doped area is formed in the first doped area.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: July 16, 2019
    Assignee: Amazing Microelectronic Corp.
    Inventors: Chih-Ting Yeh, Sung-Chih Huang, Che-Hao Chuang
  • Patent number: 10355172
    Abstract: Printed micro-LEDs have a top metal anode electrode that is relatively tall and narrow and a bottom cathode electrode. After the LED ink is cured, the bottom electrodes are in electrical contact with a conductive layer on a substrate. The locations of the LEDs are random. A thin dielectric layer is then printed between the LEDs, and a thin conductive layer, such as a nano-wire layer, is then printed over the dielectric layer to contact the anode electrodes. The top conductive layer over the tall anode electrodes has bumps corresponding with the locations of the LEDs. An omniphobic liquid is then printed which only resides in the “low” areas of the top conductive layer between the bumps. Any optical material is then uniformly printed over the resulting surface. The printed optical material accumulates only on the bump areas by adhesion and surface tension, so is self-aligned with the individual LEDs.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: July 16, 2019
    Assignee: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.
    Inventors: William Johnstone Ray, Richard A. Blanchard
  • Patent number: 10349529
    Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10347551
    Abstract: A semiconductor package comprises a resin material, a semiconductor chip in the resin material, and a metal member in the resin material. The metal member has a first surface that faces the semiconductor chip and a second surface that is opposed to the first surface. The first surface of the metal member has a plurality of first recess portions formed thereon. The first recess portions extend into the metal member and have an opening width that is less than a bottom width.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Kishi, Akito Shimizu
  • Patent number: 10347786
    Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to optical sensor that includes a substrate, an image sensor die and a light-emitting device. A first surface of the image sensor die is coupled to the substrate, and a recess is formed extending into the image sensor die from the first surface toward a second surface of the image sensor die. A light transmissive layer is formed in the image sensor die between the recess and the first surface. The optical sensor further includes a light-emitting device that is coupled to the substrate and positioned within the recess formed in the image sensor die.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 9, 2019
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Loic Pierre Louis Renard, Cheng-Lay Ang
  • Patent number: 10340219
    Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seul Ki Hong, Heon Jong Shin, Hwi Chan Jun, Min Chan Gwak
  • Patent number: 10332885
    Abstract: A capacitor includes a cell array including a plurality of cells and a fine tuning cell electrically coupled to the cell array by a first bus and a second bus. Each cell of the cell array includes a first number of fingers electrically coupled to the first and second bus, and a second number of fingers electrically coupled to the first and second bus. The fine tuning cell includes a third number of fingers electrically coupled to the first and second bus, and a fourth number of fingers electrically coupled to the first and second bus. The directional alignment of the first and second number of fingers is generally perpendicular, the directional alignment of the third and fourth number of fingers is generally perpendicular, and the second number of fingers is different than the fourth number of fingers.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventor: Jing Jing
  • Patent number: 10326012
    Abstract: A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, and a gate electrode disposed on the semiconductor substrate via a gate insulator film. The semiconductor substrate includes a first portion constituted of GaN and a second portion constituted of AlxGa(1-x)N (0<x?1). The first portion includes an n-type source region being in contact with the source electrode, an n-type drain region being in contact with the drain electrode, a p-type body region intervening between the source region and the drain region and being in contact with the source electrode, and an n-type drift region intervening between the body region and the drain region and having a carrier density that is lower than a carrier density of the drain region. The second portion includes a barrier region being in contact with each of the source electrode, the body region and the drift region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Watanabe, Hiroyuki Ueda, Tomohiko Mori