Patents Examined by Dao H. Nguyen
  • Patent number: 11152464
    Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian S. Pranatharthi Haran, Ruilong Xie, Veeraraghavan S. Basker, Robert Robison
  • Patent number: 11145706
    Abstract: A display device including a lower substrate having a display area and a pad area, a display structure disposed in the display area of the lower substrate, an upper substrate disposed on the display structure in the display area, and facing the lower substrate, pad electrodes disposed in the pad area of the lower substrate and spaced apart from each other in a first direction parallel to a top surface of the lower substrate, a conductive film member including conductive balls disposed on the pad electrodes and having a first area overlapping the pad electrodes and a second area not overlapping the pad electrodes, and a film package disposed on the conductive film member and including bump electrodes overlapping the first area of the conductive film member, in which the shape of the conductive balls disposed in the first area is different from those disposed in the second area.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 12, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joo-Nyung Jang
  • Patent number: 11139212
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first conductive element over a substrate and a second conductive element over the substrate. A dielectric region is over a top surface of the substrate and between the first conductive element and the second conductive element. An electrically conductive structure is over the first conductive element, the second conductive element, and the dielectric region.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 11133423
    Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee
  • Patent number: 11133386
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Chang-Miao Liu
  • Patent number: 11133254
    Abstract: An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Patent number: 11133440
    Abstract: Aspects include Light Emitting Diodes that have a GaN-based light emitting region and a metallic electrode. The metallic electrode can be physically separated from the GaN-based light emitted region by a layer of porous dielectric, which provides a reflecting region between at least a portion of the metallic electrode and the GaN-based light emitting region.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 28, 2021
    Assignee: BRIDGELUX, INC.
    Inventors: Frank T. Shum, William W. So, Steven D. Lester
  • Patent number: 11127700
    Abstract: An integrated circuit device includes a substrate and an integrated circuit area on the substrate. The integrated circuit area includes a dielectric stack. A cap layer is disposed on the dielectric stack. A seal ring is disposed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring to expose a sidewall of the dielectric stack. A MIM capacitor including a CTM layer and a CBM layer is disposed on the dielectric stack. A moisture blocking layer continuously covers the integrated circuit area and the MIM capacitor. The cap layer is interposed between the CTM layer and the CBM layer of the MIM capacitor and functions as a capacitor dielectric layer of the MIM capacitor. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Patent number: 11127687
    Abstract: A semiconductor package includes a lower module and an upper module stacked on the lower module. Each of the lower module and the upper module includes a semiconductor chip, an interposing bridge, an encapsulant, and a redistributed line (RDL). The interposing bridge is configured to include a first through via and a second through via. The upper module is laterally offset, relative to the lower module, by an array pitch of the first and second through vias such that the first through via of the upper module overlaps with and is connected to the second through via of the lower module.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Bok Kyu Choi
  • Patent number: 11127834
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 21, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC
    Inventors: Jiehui Shu, Sipeng Gu, Halting Wang
  • Patent number: 11121148
    Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang Min Kim, Jin Hyuk Kim, Jung Tae Sung, Joong Shik Shin, Sung Hyung Lee
  • Patent number: 11121178
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include: row lines; column lines intersecting the row lines; memory cells located in intersection regions of the row lines and the column lines, the memory cells including upper and lower electrodes; and interface layers located between the lower electrodes of the memory cells and the row lines, the interface layers having a width narrower than that of the row lines.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyun Jin Lee, Young Seok Ko, Jung Hun Lee, Hyun Min Lee
  • Patent number: 11121225
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate electrode overlies a substrate between a source region and a drain region. A drift region is arranged laterally between the gate electrode and the drain region. A plurality of inter-level dielectric (ILD) layers overlie the substrate. The plurality of ILD layers includes a first ILD layer underlying a second ILD layer. A plurality of conductive interconnect layers is disposed within the plurality of ILD layers. The field plate extends from a top surface of the first ILD layer to a point that is vertically separated from the drift region by the first ILD layer. The field plate is laterally offset the gate electrode by a non-zero distance in a direction toward the drain region. The field plate includes a same material as at least one of the plurality of conductive interconnect layers.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Ming-Ta Lei, Yu-Chang Jong
  • Patent number: 11107930
    Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Junichi Koezuka, Takashi Hamochi
  • Patent number: 11107751
    Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Loke Yip Foo, Choong Kooi Chee
  • Patent number: 11107918
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, an N-type well region over the semiconductor substrate, a FDSOI transistor formed over the N-type well region, a first shallow trench isolation (STI) region over the N-type well region, a first N-type doped region over the N-type well region, a second STI region over the semiconductor substrate, a first P-type doped region over the semiconductor substrate, and a first interconnection element over the first P-type doped region. The first P-type doped region is separated from the first N-type doped region by the second STI region. The first interconnection element is configured to connect the first P-type doped region to a ground. No interconnection element is formed over the first N-type doped region so that the first N-type doped region and the N-type well region are floating.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 31, 2021
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Jen-Wei Ko, Zheng Zeng, Sheng-Yi Huang
  • Patent number: 11101312
    Abstract: A semiconductor apparatus comprising: a first semiconductor component including a first semiconductor layer and a first insulation film; and a second semiconductor component including a second semiconductor layer and a second insulation film, wherein the first semiconductor component and the second semiconductor component are bonded to each other by each of a plurality of first electric conductor portions provided in the first insulation film and each of a plurality of second electric conductor portions provided in the second insulation film, each of the plurality of first electric conductor portions is constituted by one pad surrounded by the first insulation film and N vias bonded to the one pad so as to be positioned between the one pad and the first semiconductor layer, and a volume VTR of the one pad and a total volume VTH of the N vias satisfy VTR/VTH?N.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 24, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Hiroaki Kobayashi, Tsutomu Tange, Akihiro Shimizu
  • Patent number: 11101324
    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 24, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Bin-Siang Tsai, Ya-Jyuan Hung, Chin-Chia Yang, Ting-An Chien
  • Patent number: 11088100
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 10, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Patent number: 11088281
    Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Pei-Yu Wang, Sai-Hooi Yeong