Patents Examined by David A. Hey
  • Patent number: 4603468
    Abstract: In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.
    Type: Grant
    Filed: September 28, 1984
    Date of Patent: August 5, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Hon W. Lam
  • Patent number: 4602420
    Abstract: A method of manufacturing a semiconductor device including the steps of forming a passivation film, which has an opening exposing that region of the interlayer insulation film formed on the fuse element, which corresponds to the region to be melted of fuse element, melting the region of the fuse element to be melted by radiating a laser beam on the exposed region of the interlayer insulation film through the opening, and the step of forming a protective resin layer on the whole main surface of the resultant structure after melting is completed.
    Type: Grant
    Filed: December 13, 1984
    Date of Patent: July 29, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shozo Saito
  • Patent number: 4601097
    Abstract: A method of manufacturing a thin film transistor array is simplified by processes to form source and drain electrodes at least of ITO film for pixel electrodes on a gate insulating film covering gate electrode and to form islands of an amorphous semiconductor film and a light shield film in the same masking process on the source and the drain electrodes.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: July 22, 1986
    Assignee: Seiko Instruments & Electronics Ltd.
    Inventor: Masafumi Shimbo
  • Patent number: 4596069
    Abstract: The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: June 24, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 4596070
    Abstract: The disclosure relates to a semiconductor substrate having an active area for formation of an IMPATT device which is formed as a plurality of separated fingers having a common n+ region to spread the area over which the IMPATT is disposed and which provides such additional area for dissipation of heat through the substrate.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: June 24, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 4596071
    Abstract: A method of making semiconductor devices having fine dielectric element isolation regions is disclosed. The method comprises the steps of preparing a semiconductor substrate of one conductivity type which is in a high impurity concentration; forming on the surface of the semi-conductor substrate an epitaxial layer having the same conductivity type as that of the semiconductor substrate in a low impurity concentration; etching off selected regions of the epitaxial layer so as to form islands of the epitaxial layer; forming a CVD oxide layer all over the surface of the structure obtained by the steps; applying high-molecular material film all over the surface of the oxide layer; and removing both the oxide layer and the high-molecular material film so as to expose the surface of the islands, whereby fine element isolation regions of the oxide layer are obtained between the islands.
    Type: Grant
    Filed: August 15, 1984
    Date of Patent: June 24, 1986
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Kita
  • Patent number: 4593456
    Abstract: A thermal detector array includes a substrate layer with a pyroelectric layer attached to the substrate, a plurality of detector regions being defined in the pyroelectric layer by openings through the layer. An array of cavities in the substrate surface separates the detector regions from the surface. First and second electrodes are placed on opposite sides of each detector region or on a single side in a coplanar embodiment. The array is joined to a signal processing device by means of corresponding metallic contacts on the pyroelectric layer and the processing device.
    Type: Grant
    Filed: April 10, 1985
    Date of Patent: June 10, 1986
    Assignee: Rockwell International Corporation
    Inventor: Derek T. Cheung
  • Patent number: 4593453
    Abstract: The invention relates to the process for manufacturing and the structure of stacked transistors on a silicon substrate wherein a polysilicon layer is employed which is recrystallized and delineated to form the gate for one transistor and the source, channel and drain for the complementary transistor which is totally formed using isolating field oxide as its substrate.
    Type: Grant
    Filed: June 18, 1984
    Date of Patent: June 10, 1986
    Assignee: Rockwell International Corporation
    Inventors: Matthias L. Tam, Frank Z. Custode
  • Patent number: 4592128
    Abstract: A poly layer on a substrate is covered with nitride. A reverse tone load implant mask and etch opens an area, which is then boron implanted. Controlled oxidation follows to grow oxide on the boron-doped region only, thereby thinning the poly there. Strip the nitride and then dope the poly layer. The oxide shields the boron-doped region from further substantial doping. Next, apply a poly definition photoresist mask. Etch the exposed oxide and poly to define a poly line having a boron-doped resistor therein. The difference in etch rates between heavily doped and lightly doped poly is compensated for by the adjustment of thickness of the boron-doped region. Hence, the etch for both types of poly concludes at about the same time, leaving the underlying layers substantially intact. Sources and drains may be implanted thereafter without an additional load implant mask.
    Type: Grant
    Filed: June 4, 1984
    Date of Patent: June 3, 1986
    Assignee: Inmos Corporation
    Inventor: Ronald R. Bourassa
  • Patent number: 4590664
    Abstract: The thick oxide over the surface portion of a P/N junction of a reference diode is removed, a thin oxide is grown thereon, and a contaminated shield layer is formed on the thin oxide. In addition to improving the reversed biased diode, the same method improves the forward biased emitter-base surface junction of a vertical bipolar transistor. The shield layer may be biased separate from the transistor.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: May 27, 1986
    Assignee: Harris Corporation
    Inventors: John S. Prentice, Gabriel J. Uscategui
  • Patent number: 4588455
    Abstract: Planar diffusion sources are provided wherein the source is a wafer of inert material, preferably silicon or silicon dioxide and wherein the wafer acts as a substrate for a surface coating comprising a salt, preferably the oxide, of the dopant element. An inert oxide such as aluminum oxide or silicon dioxide may also be included in the coating. When applied to the substrate as a paste or slurry and fired to suitable temperatures, the dopant oxide coating tightly adheres to the substrate wafer. The coated diffusion source is placed alongside semi-conductor wafers in a diffusion furnace; where, at diffusion temperatures, the dopant element volatilizes and diffuses into the surface of the semi-conductor material. The diffusion source can be reused numerous times.
    Type: Grant
    Filed: August 15, 1984
    Date of Patent: May 13, 1986
    Assignee: Emulsitone Company
    Inventor: Milton Genser
  • Patent number: 4584763
    Abstract: A one mask technique for making substrate contact from the top surface of an integrated circuit device. A thin ion implanted region of one conductivity type is formed over the entirety of a major surface of the semiconductor substrate. By lithography and etching, a shallow etched region is formed to a depth below the region of the first conductivity type at the substrate surface in an area designated for substitute contacting. A region of a second conductivity type is then formed at the central portion of the etched region. The substrate is then heated to form a buried collector region of the first conductivity type and a portion of the reach-through region of the second conductivity type in the substrate. An epitaxial layer is next formed on the major surface of the substrate. A base region of the second conductivity type for the integrated circuit is then formed.
    Type: Grant
    Filed: December 15, 1983
    Date of Patent: April 29, 1986
    Assignee: International Business Machines Corporation
    Inventors: Chakrapani G. Jambotkar, Shashi D. Malaviya
  • Patent number: 4584762
    Abstract: The invention is a transistor or array thereof and method for producing same in VLSI dimensions on a silicon substrate doped P or N type by forming intersecting slots in spaced apart relation across the substrate to define semiarrays of V shaped intermediate regions which will become transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divided the semiarrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation.
    Type: Grant
    Filed: December 5, 1983
    Date of Patent: April 29, 1986
    Assignee: Rockwell International Corporation
    Inventor: Sidney I. Soclof
  • Patent number: 4583283
    Abstract: An improved power semiconductor device and manufacturing method are described wherein the external, thermally conducting, heat transfer face of the device is electrically insulated by a glassy dielectric which is intimately bonded directly to the conductive heat spreader supporting the semiconductor die. By forming the exposed corners of the heat spreader to be substantially smooth curved surfaces having a predetermined minimum radius of curvature greater than the thickness of the glassy dielectric, formation of a ridge of glass at the corners and edges of the heat spreader is avoided. For ease of assembly the piece parts are initially substantially flat and parallel. A molding compound of controlled shrinkage is used to avoid distorting the substantially flat smooth insulated heat transfer face which remains exposed in the encapsulated device.
    Type: Grant
    Filed: January 22, 1985
    Date of Patent: April 22, 1986
    Assignee: Motorola, Inc.
    Inventors: Jerry M. Dubois, Keith G. Spanjer
  • Patent number: 4580331
    Abstract: The invention provides a unique VLSI dimensioned PNP-type transistor and method of making the same wherein hundreds of such transistors may be fabricated on a single chip with each transistor comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Slots made in the substrate permit angle evaporation of etch-resist to protect the active region while it is disconnected from the substrate by etching therebeneath via the slots.
    Type: Grant
    Filed: December 5, 1983
    Date of Patent: April 8, 1986
    Assignee: Rockwell International Corporation
    Inventor: Sidney I. Soclof
  • Patent number: 4577398
    Abstract: A method of attaching a semiconductor chip to a mounting surface is disclosed. A solder barrier is applied to the mounting surface, and a preform of solder is located within the solder barrier. The preform is heated and then cooled in a vacuum to preflow the solder and secure the solder to the mounting surface substantially without voids. The semiconductor chip is then placed over the preflowed solder, which is reheated and then recooled in a vacuum to secure the chip to the mounting surface.
    Type: Grant
    Filed: September 7, 1984
    Date of Patent: March 25, 1986
    Assignee: Trilogy Computer Development Partners, Ltd.
    Inventors: John W. Sliwa, Roy J. Burt, Chune Lee, John MacKay, Cindy A. Johnson
  • Patent number: 4575919
    Abstract: A method of making a ridge waveguide laser with the ridge being grown through a stripe opened in an oxide layer covering one of the cladding layers is described. In one embodiment, the cladding layer is corrugated and the ridge waveguide laser is a distributed feedback laser.
    Type: Grant
    Filed: May 24, 1984
    Date of Patent: March 18, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Ralph A. Logan, Won-Tien Tsang
  • Patent number: 4574467
    Abstract: CMOS transistors are fabricated in a P substrate using N- well regions. These wells are positioned to prevent aluminum spiking in the N channel devices. After P guard rings are formed for both P and N channel devices, additional masking and implantation are performed to produce N guard rings in the P channel devices. Before the transistors are formed, an implantation of P type impurities is performed causing the P channel devices, when they are formed, to have a PMOS buried channel.
    Type: Grant
    Filed: August 31, 1983
    Date of Patent: March 11, 1986
    Assignee: Solid State Scientific, Inc.
    Inventors: Mark A. Halfacre, David S. Pan, Wing K. Huie
  • Patent number: 4574469
    Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: March 11, 1986
    Assignee: Motorola, Inc.
    Inventors: Sal Mastroianni, Carroll Casteel, Terry S. Hulseweh
  • Patent number: 4569124
    Abstract: A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.
    Type: Grant
    Filed: May 22, 1984
    Date of Patent: February 11, 1986
    Assignee: Hughes Aircraft Company
    Inventors: David B. Rensch, John Y. Chen