Patents Examined by David A. Hey
  • Patent number: 4541169
    Abstract: Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching procedures to accommodate differences in stud elevation and in stud size, are features which provide substantial planarity in the successive levels.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: September 17, 1985
    Assignee: International Business Machines Corporation
    Inventor: Thomas A. Bartush
  • Patent number: 4541168
    Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: September 17, 1985
    Assignee: International Business Machines Corporation
    Inventors: John R. Galie, George R. Goth, Thomas A. Hansen, Robert T. Villetto, Jr.
  • Patent number: 4538344
    Abstract: An interconnection structure including an electrode/wiring layer can be formed on a semiconductor substrate by forming on the semiconductor substrate an insulating structure having at least one recess in a surface thereof. At least one polycrystalline silicon layer is formed to fill the recess of the insulating structure. Then, an aluminum layer is formed to cover a surface of the insulating structure and a surface of the polycrystalline silicon layer. The polycrystalline silicon in the polycrystalline silicon layer and the aluminum in a portion of the aluminum layer which corresponds to the polycrystalline silicon layer are converted into a single alloy by heating to form an electrode/wiring layer comprising the single alloy in the recess and connected to a remaining portion of the aluminum layer.
    Type: Grant
    Filed: February 21, 1984
    Date of Patent: September 3, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Katsuya Okumura, Masaaki Ueda
  • Patent number: 4536951
    Abstract: A method of forming a layered structure, which method comprises depositing a first metal layer on a substrate, depositing a barrier layer on the first metal layer, depositing a second metal layer on the barrier layer, forming a first masking pattern on the second metal layer, etching the first and second metal layers and the barrier layer in accordance with the first masking pattern, removing the first masking pattern, forming a second masking pattern on the second metal layer, etching the second metal layer in accordance with the second masking pattern, removing the second masking pattern, depositing a dielectric layer having a thickness sufficient to cover the second metal layer, etching the dielectric layer to expose the second metal layer, and depositing on the etched dielectric layer and exposed second metal layer a further metal layer to contact the exposed second metal layer.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: August 27, 1985
    Assignee: Plessey Overseas Limited
    Inventors: Stephen J. Rhodes, Raymond E. Oakley
  • Patent number: 4535531
    Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure.
    Type: Grant
    Filed: March 22, 1982
    Date of Patent: August 20, 1985
    Assignee: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Jack A. Dorler, Santosh P. Gaur, John S. Lechaton, Joseph M. Mosley, Gurumakonda R. Srinivasan
  • Patent number: 4534105
    Abstract: An improved method of grounding a pellet mounting pad is disclosed wherein the ground wire is bonded to one of the structural support members of the mounting pad rather than to the surface of the pad itself.
    Type: Grant
    Filed: August 10, 1983
    Date of Patent: August 13, 1985
    Assignee: RCA Corporation
    Inventor: Raymond K. Reusch
  • Patent number: 4527325
    Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the sacrificial layer is then also removed through a different etching step.
    Type: Grant
    Filed: December 23, 1983
    Date of Patent: July 9, 1985
    Assignee: International Business Machines Corporation
    Inventors: Henry J. Geipel, Jr., Charles A. Schaefer, Francis R. White, John M. Wursthorn
  • Patent number: 4526629
    Abstract: One or more monolayers of cerium arrayed on the surface of a niobium metal acts as a catalyst to oxidation of the niobium at ambient temperature and results in a very thin, very high quality insulating layer which may be configured by patterning of the catalyst. Significant amounts of Nb.sub.2 O.sub.5 are formed at pressures as low as 6.6.times.10.sup.-6 Pa, promoted by the presence of the cerium. This catalytic activity is related to the trivalent to tetravalent valence change of the cerium during oxidation. The kinetics of Nb.sub.2 O.sub.5 formation beneath the oxidized cerium shows two stages:the first stage is fast growth limited by ion diffusion;the second stage is slow growth limited by electron tunneling.Other catalytic rare earths usable instead of cerium are terbium and praseodymium; other substrate materials usable instead of niobium are aluminum, hafnium, silicon and tantalum, or oxidizable alloys thereof.
    Type: Grant
    Filed: May 15, 1984
    Date of Patent: July 2, 1985
    Assignee: International Business Machines Corporation
    Inventors: Ernst-Eberhard Latta, Maria Ronay
  • Patent number: 4524508
    Abstract: A method of manufacturing a semiconductor device comprises forming a mask of a predetermined pattern on a first conductive layer (3) deposited over a semiconductor substrate (1) and etching physically first conductive layer so that the side surfaces thereof are substantially perpendicular to a surface of the semiconductor substrate. After removing the mask on the pattern, a first insulating layer (7) is deposited over the whole upper surface of the semiconductor substrate including the first conductive layer. A physical etching is made over the first insulating layer until the surface of the semiconductor substrate is exposed, so that a portion (7a) of the first insulating layer (7) is left in a stepped portion of the side surfaces of the first conductive layer. Then, a second insulating layer (5) is formed over a whole upper surface of the semiconductor substrate including the portion (7a) of the insulating layer and the first conductive layer.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: June 25, 1985
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinichi Sato
  • Patent number: 4523368
    Abstract: A field effect device having a gate over a portion of a surface of a semiconductor disposed between a source region and a drain region and including a buried doped region having a conductivity type opposite the conductivity type of the semiconductor formed in the semiconductor under, and spaced from such portion of the surface of the semiconductor. The buried doped region is electrically connected to the gate electrode. With such arrangement a field effect device is formed with a connecting channel having a shallow depth in the semiconductor between the gate and the buried doped layer. A method for fabricating field effect devices is also disclosed, such method including the step of forming a pair of masking surfaces of insulating material on the surface of the semiconductor. An ion implantation masking layer is formed between the pair of masking surfaces to enable the selective implantation of particles in the semiconductor to establish the source and drain regions.
    Type: Grant
    Filed: April 24, 1984
    Date of Patent: June 18, 1985
    Assignee: Raytheon Company
    Inventor: Wolfgang M. Feist
  • Patent number: 4520552
    Abstract: A semiconductor device with deep grid accessible via the surface having a silicon substrate and comprising U-shaped grooves. The upper parts of the side walls of these grooves are insulated by a silica layer and the lower parts of these grooves connect up with overdoped zones. Polycrystalline silicon provides ohmic contact between selected positions on the upper face of the transistor and the grid layer.
    Type: Grant
    Filed: January 16, 1984
    Date of Patent: June 4, 1985
    Assignee: Thomson-CSF
    Inventors: Jacques Arnould, Eugene Tonnel
  • Patent number: 4517730
    Abstract: The invention relates to a method of providing a small-sized opening for manufacturing semiconductors, such as field effect transistors having an aligned gate in the submicron range, as well as to transistors obtained by this method. In general, the invention consists in that an intermediate window is formed to provide the aligned gate in a semiconductor, which window is eliminated after forming the gate. The invention is used in the field of electronics, more particularly, in the manufacture of semiconductor elements.
    Type: Grant
    Filed: August 31, 1983
    Date of Patent: May 21, 1985
    Assignee: U.S. Philips Corporation
    Inventor: Didier S. Meignant
  • Patent number: 4516312
    Abstract: A method for constructing delay circuits in a master slice IC formed on a semiconductor substrate. The master slice IC comprises regularly arranged MIS transistors having gate electrodes. The MIS transistors includes various logic circuits. A delay circuit is formed between two logic circuits. The delay circuit comprises a resistor and a capacitor. The resistor is constructed using the resistances of the gate electrodes by sequentially connecting the gate electrodes between two logic circuits. The capacitor is constructed using capacitances formed between the gate electrodes and the semiconductor substrate. A precise delay time of a delay circuit having a small area can be obtained.
    Type: Grant
    Filed: February 10, 1982
    Date of Patent: May 14, 1985
    Assignee: Fujitsu Limited
    Inventor: Masayoshi Tomita
  • Patent number: 4517027
    Abstract: A reuseable collector for use in a process for the bulk production of alloy by deposition from the vapor phase. The collector employs a coating of solder alloy on the deposition surface such that after deposition has been completed the solder alloy may be melted and the deposited alloy removed from the collector without the necessity of destroying the collector.
    Type: Grant
    Filed: December 15, 1981
    Date of Patent: May 14, 1985
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Robert L. Bickerdike, Garyth Hughes
  • Patent number: 4512073
    Abstract: A process for forming reliable contacts in a VLSI device wherein, after the source and drain regions have been formed, the contact openings are formed and the source and drain regions redoped. A heat treatment step anneals surface damage and causes lateral migration of the implanted ions to preclude the contact from forming a short circuit between the doped region and the substrate exposed as a result of any misalignment of the contact openings. As an added benefit, the process also prevents the contact from "spiking" through the doped region to the underlying substrate.
    Type: Grant
    Filed: February 23, 1984
    Date of Patent: April 23, 1985
    Assignee: RCA Corporation
    Inventor: Sheng T. Hsu
  • Patent number: 4510671
    Abstract: A transducer structure is disclosed which comprises a single crystal semiconductor diaphragm dielectrically isolated by a layer of silicon dioxide from a single crystal gage configuration. The methods depicted employ high dose oxygen which is ion implanted into a monocrystalline wafer to form a buried layer of silicon dioxide with the top surface of the wafer being monocrystalline silicon. An additional layer of silicon is epitaxially grown on the top surface of the wafer to enable the etching or formation of a desired gage pattern.
    Type: Grant
    Filed: November 21, 1983
    Date of Patent: April 16, 1985
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Anthony D. Kurtz, Timothy A. Nunn, Joseph R. Mallon
  • Patent number: 4510677
    Abstract: A case, manufactured and possibly stored in a semi-finished condition, comprising connecting lugs disposed flat after being sealed in a block of plastic material. Only then are the lugs cut out and bored if necessary, to a chosen shape and then, if need be, bent upwardly. To facilitate this bending, it is provided that the block comprises faces recessed with respect to the vertical line of the edges of a base.
    Type: Grant
    Filed: April 1, 1982
    Date of Patent: April 16, 1985
    Assignee: Thomson CSF
    Inventor: Yoland Collumeau
  • Patent number: 4506435
    Abstract: A method is described for forming the recessed dielectric isolation in a silicon substrate involves first forming trenches which may be less than about 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region is formed in the substrate prior to the deposition of an epitaxial layer thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches are then oxidized in an oxidizing ambient to form a silicon dioxide layer thereon.
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: March 26, 1985
    Assignee: International Business Machines Corporation
    Inventors: William A. Pliskin, Jacob Riseman, Joseph F. Shepard
  • Patent number: 4506434
    Abstract: A method for producing semiconductor devices having a substrate, element fabrication areas formed in the substrate and isolation areas surrounding the element fabrication areas. The method comprises forming a thermal strain absorbing layer on the top surface of the element fabrication areas, forming at least one groove in an area which is to become the isolation areas, inlaying an insulator in the at least one groove, and annealing the insulator to make the density thereof uniform.
    Type: Grant
    Filed: September 3, 1982
    Date of Patent: March 26, 1985
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Ogawa, Nobuo Toyokura
  • Patent number: 4506436
    Abstract: A method for reducing the susceptibility of integrated circuit dynamic memory devices to environmentally produced radiation, such as alpha particles, in which a buried layer, having a majority carrier concentration substantially equal to or greater than the concentration of free carriers generated by the radiation and being between one and four orders of magnitude greater concentration than that of the semiconductor substrate, is ion implanted within a few microns of the substrate surface after at least one major high temperature processing step in the manufacturing process has been completed.
    Type: Grant
    Filed: December 21, 1981
    Date of Patent: March 26, 1985
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Bakeman, Jr., Robert M. Quinn