Abstract: An image sensor includes a sensor pixel. The sensor pixel includes a first transistor coupled between a first power source and a first node, where the first transistor is turned on in response to a first control signal, a light-sensing element coupled between the first node and a second power source, where the light-sensing element generates photocharges in response to incident light, a storage capacitor coupled in parallel to the light-sensing element between the first node and the second power source, and an amplifier including a plurality of transistors coupled in series between the first power source and an output line, where the amplifier outputs a sensing signal corresponding to a voltage of the first node in response to a first driving signal.

Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

Abstract: A device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The package cover generally has an inlet opening and an outlet opening disposed there through. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The device package may include a material layer between the package cover and the cold plate. The cold plate may include a patterned first side and an opposite second side. The patterned first side may include a base surface and sidewalls extending downward from the base surface, where the base surface is spaced apart from the semiconductor device to collectively define a coolant channel. Here, the coolant channel is in fluid communication with the inlet opening and the outlet opening through openings disposed through respective portions of the material layer.

Abstract: A method for manufacturing a semiconductor device including a TiN film. The method comprises: supplying TiCl4 gas to a substrate; purging the TiCl4 gas; supplying NH3 gas to the substrate; purging the NH3 gas; and supplying an inhibitor that inhibits adsorption of TiCl4 or NH3 to the substrate. A plurality of cycles each including the supplying the TiCl4 gas, the purging the TiCl4 gas, the supplying the NH3 gas, and the purging the NH3 gas are performed, at least a part of the plurality of cycles includes the supplying the inhibitor, and after the supplying the inhibitor is performed, the supplying the TiCl4 gas or the supplying the NH3 gas is performed without purging the inhibitor, or, after purging the inhibitor for a shorter time than the purging the TiCl4 gas or the purging the NH3 gas, the supplying the TiCl4 gas or the supplying the NH3 gas is performed.

Abstract: A packaged current sensor integrated circuit includes a primary conductor having an input portion and an output portion configured to carry a current to be measured by one or more magnetic sensing elements supported by a semiconductor die adjacent to the primary conductor. A method of fabricating the packaged current sensor integrated circuit includes partially encasing the lead frame in a first mold material, applying an insulator to one or more die attach pads, attaching a die to the insulator, electrically connecting the die to secondary leads, and providing a second mold to the subassembly. The package is configured to provide increased voltage isolation.

Abstract: A semiconductor device includes a semiconductor element, a first lead, a second lead and a connection lead. The semiconductor element includes an electron transit layer formed of a nitride semiconductor, an element obverse face and an element reverse face that are arranged to face opposite to each other in a thickness direction, and a gate electrode, a source electrode and a drain electrode that are disposed on the element obverse face. The drain electrode is bonded to the first lead. The source electrode is bonded to the second lead. The connection lead is connected to the second lead and disposed on the element reverse face so as to overlap with the semiconductor element as viewed in the thickness direction. The connection lead provides a conduction path for a principal current subjected to switching.

Abstract: An apparatus for injecting solder material in via holes located in a top surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the top surface of the wafer, and at least one aperture for injecting the solder material though the injection head into the via holes. The apparatus further includes an evacuating device connected to the injection head for evacuating gas from the via holes. The injection head has a chamfer part on an edge of a contact surface contacting the top surface of the wafer.

Abstract: A bonding wire includes a core material of Cu or Cu alloy, and a coating layer containing a conductive metal other than Cu on a surface of the core material. In a concentration profile in a depth direction of the wire obtained, an average value of sum of a Pd concentration CPd (atomic %) and an Ni concentration CNi (atomic %) for measurement points in the coating layer is 50 atomic % or more, an average value of a ratio of CPd to CNi for measurement points in the coating layer is from 0.2 to 20 and a thickness of the coating layer is from 20 nm to 180 nm. An Au concentration CAu at a surface of the wire is from 10 atomic % to 85 atomic %. An average size of crystal grains in a circumferential direction of the wire is from 35 nm to 200 nm.

Abstract: Recesses may be formed in portions of an ILD layer of a semiconductor device in a highly uniform manner. Uniformity in depths of the recesses may be increased by configuring flows of gases in an etch tool to promote uniformity of etch rates (and thus, etch depth) across the semiconductor device, from semiconductor device to semiconductor device, and/or from wafer to wafer. In particular, the flow rates of gases at various inlets of the etch tool may be optimized to provide recess depth tuning, which increases the process window for forming the recesses in the portions of the ILD layer. In this way, the increased uniformity of the recesses in the portions of the ILD layer enables highly uniform capping layers to be formed in the recesses.

Abstract: Embodiments may relate to a microelectronic package comprising that includes a solder thermal interface material (STIM). The STIM may include indium and a dopant material which may provide a number of benefits to the STIM. The STIM may physically and thermally couple a die and an integrated heat spreader (IHS). Other embodiments may be described or claimed.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

Abstract: The light-emitting device includes a first light-emitting part including a first light-emitting element and a first light-transmissive member disposed over the first light-emitting element, a second light-emitting part including a second light-emitting element and a second light-transmissive member disposed over the second light-emitting element, a first light-shielding member disposed between a first lateral surface of the first light-transmissive member and a second lateral surface of the second light-transmissive member and containing a first additive, and a second light-shielding member disposed between a first element lateral surface of the first light-emitting element and a second element lateral surface of the second light-emitting element, holding the first light-emitting part and the second light-emitting part, and containing a second additive having a higher thermal conductivity than the first additive.

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

Abstract: A method of manufacturing a semiconductor device includes forming a polymer mixture over a substrate, curing the polymer mixture to form a polymer material, and patterning the polymer material. The polymer mixture includes a polymer precursor, a photosensitizer, a cross-linker, and a solvent. The polymer precursor may be a polyamic acid ester. The cross-linker may be tetraethylene glycol dimethacrylate. The photosensitizer includes 4-phenyl-2-(piperazin-1-yl)thiazole. The mixture may further include an additive.

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.

Abstract: A material structure for silicon-based gallium nitride microwave and millimeter-wave devices and a manufacturing method thereof are provided. The material structure includes: a silicon substrate; a dielectric layer of high thermal conductivity, disposed on an upper surface of the silicon substrate, and an uneven first patterned interface being formed between the dielectric layer and the silicon substrate; a buffer layer, disposed on an upper surface of the dielectric layer, and an uneven second patterned interface being formed between the buffer layer and the dielectric layer; a channel layer, disposed on an upper surface of the buffer layer; and a composite barrier layer, disposed on an upper surface of the channel layer. In the material structure, the uneven patterned interfaces increase contact areas of the interfaces, a thermal boundary resistance and a thermal resistance of device are reduced, and a heat dissipation performance of device is improved.

Abstract: There is provided a metal-coated Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the metal-coated Al bonding wire is operated. The bonding wire includes a core wire of Al or Al alloy, and a coating layer of Ag, Au or an alloy containing them formed on the outer periphery of the core wire, and the bonding wire is characterized in that when measuring crystal orientations on a cross-section of the core wire in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction. Preferably, the surface roughness of the wire is 2 ?m or less in terms of Rz.

Abstract: The present disclosure provides fan-out LED packaging structures and methods. The fan-out LED packaging structure at least comprises: an LED wafer, a packaging layer, a first redistribution layer, an IC control chip module, and a second redistribution layer. The LED wafer and the IC control chip module use metal wires of the first and second redistribution layers and metal-plated holes of the packaging layer to lead out and to control the LED wafer and the IC control chip. The present disclosure also provides fan-out LED packaging methods. The methods adopt metal plating in place of wire bonding, and adopt PI dielectric layers and rewiring layers in place of a base substrate, thus effectively reducing the LED package size.

Abstract: A bonding wire includes a core material of Cu or Cu alloy, and a coating layer containing a conductive metal other than Cu on a surface of the core material. In a concentration profile in a depth direction of the wire obtained, an average value of sum of a Pd concentration CPd (atomic %) and an Ni concentration CNi (atomic %) for measurement points in the coating layer is 50 atomic % or more, an average value of a ratio of CPd to CNi for measurement points in the coating layer is from 0.2 to 20 and a thickness of the coating layer is from 20 nm to 180 nm. An Au concentration CAu at a surface of the wire is from 10 atomic % to 85 atomic %. An average size of crystal grains in a circumferential direction of the wire is from 35 nm to 200 nm.