Patents Examined by David A. Zarneke
  • Patent number: 10438882
    Abstract: Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventor: Eng Huat Goh
  • Patent number: 10438929
    Abstract: According to one embodiment, M (M represents an integer of 2 or larger) semiconductor chips and through electrodes for N (N represents an integer of 2 or larger) channels are provided. The M semiconductor chips are stacked in sequence. The through electrodes are embedded in the semiconductor chips to connect electrically the semiconductor chips in the direction of stacking. The connection destination of the through electrodes are exchanged between one or more upper and lower layers of the semiconductor chips.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshiyuki Kouchi, Masaru Koyanagi
  • Patent number: 10424540
    Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 24, 2019
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Po-Han Lee, Chia-Ming Cheng, Hsin-Yen Lin
  • Patent number: 10418396
    Abstract: Implementations of semiconductor packages may include: an image sensor; an optically transmissive transparent coating directly coupled to the image sensor; and a glass lid coupled directly coupled to the optically transmissive coating. An entire surface of the glass may be directly coupled to an entire surface of the optically transmissive adhesive coating.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Weng-Jin Wu
  • Patent number: 10418311
    Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
  • Patent number: 10402620
    Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung Ho Kim, Da Hee Kim, Joon Sung Kim, Joo Young Choi, Hee Sook Park, Tae Wook Kim
  • Patent number: 10403562
    Abstract: A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Ho Baek, Joo Hwan Jung, Yoo Rim Cha, Young Sik Hur, Jung Chul Gong
  • Patent number: 10399170
    Abstract: A die attachment apparatus for attaching a semiconductor die onto a substrate having a metallic surface comprises a material dispensing station for dispensing a bonding material onto the substrate and a die attachment station for placing the semiconductor die onto the bonding material which has been dispensed onto the substrate. An activating gas generator positioned before the die attachment station introduces activated forming gas onto the substrate in order to reduce oxides on the substrate.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 3, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Kui Kam Lam, Pingliang Tu, Zhao Yang, Jun Qi, Chun Hung Samuel Ip
  • Patent number: 10395984
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
  • Patent number: 10388601
    Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: William R. Brown, Jenna L. Russon, Tim H. Bossart, Brian R. Watson, Nikolay A. Mirin, David A. Kewley
  • Patent number: 10371717
    Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Patent number: 10374191
    Abstract: Provided is a display device, comprising a display panel which comprises a first area and a second area located around the first area; and an under-panel sheet which is located under the display panel and overlaps the first area and the second area, wherein the under-panel sheet comprises a buffer member and a strength reinforcing member, wherein the strength reinforcing member is thinner than the buffer member, and a ratio of a thickness of the buffer member to a thickness of the strength reinforcing member is 3 to 6 times.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 6, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youn Hwan Jung, Kyu Han Bae, Jae Lok Cha, Kang Yong Lee
  • Patent number: 10374065
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 6, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Haiyang Zhang, Yan Wang
  • Patent number: 10366958
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Patent number: 10347571
    Abstract: In one example, a device having integrated package interference isolation includes a ground pad, an integrated circuit device die secured to the ground pad, a substrate secured to the ground pad, at least one a high-frequency, high-power semiconductor device secured to a top mounting surface of the substrate. For electromagnetic isolation, the integrated circuit device die includes a top metal, and the substrate includes a metal via electrically coupled to a metal trace that extends on the top mounting surface of the substrate. The device package also includes a number of ground pad bonding wires that electrically couple the redistribution layer of the integrated circuit device die and the metal trace to the ground pad. The redistribution layer of the integrated circuit device die and the metal trace and via of the substrate help to shield electromagnetic radiation between components in the device package.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: July 9, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: Andrzej Rozbicki, Chi Mo, Cristiano Bazzani
  • Patent number: 10326028
    Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Sinan Goktepeli, Peter Graeme Clarke
  • Patent number: 10319668
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung
  • Patent number: 10297564
    Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Georg Meyer-Berg
  • Patent number: 10297520
    Abstract: A manufacturing method of a semiconductor device includes: forming a mark on a surface of a semiconductor wafer, at least a part of the mark being disposed in a planned-peripheral region, the planned-peripheral region being located around a respective planned-element region where a semiconductor element is to be formed; forming the semiconductor element in the planned-element region using the mark; forming a film that extends across a range including the planned-element region or the planned-peripheral region in the surface so as to cover at least a part of the mark with the film, after forming the semiconductor element; and after forming the film, cutting the semiconductor wafer along a dicing region, the dicing region located around the planned-peripheral region.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 21, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Katsutoshi Narita
  • Patent number: 10290584
    Abstract: An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu