Patents Examined by David A. Zarneke
  • Patent number: 10971465
    Abstract: The present disclosure provides a driving chip, a display substrate, a display device and a method for manufacturing a display device. The driving chip according to the present disclosure includes a substrate; and a plurality of connecting bumps and a plurality of supporting bumps disposed on the substrate. The plurality of connecting bumps include at least one set of connecting bumps arranged along a first direction, and the plurality of supporting bumps include the supporting bump that is located between the adjacent connecting bumps arranged along the first direction.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 6, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liqiang Chen, PaoMing Tsai, Jianwei Li, Dejun Bu, Shuang Du, Can Zheng
  • Patent number: 10964595
    Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ping Wang, Ming-Kai Liu, Kai-Chiang Wu
  • Patent number: 10957583
    Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; an ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10957664
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Jiun Wu, Mingni Chang, Ming-Yih Wang, Yinlung Lu
  • Patent number: 10950562
    Abstract: A microwave electronic component comprising a substrate having top and bottom substrate surfaces; the substrate comprising an aperture between the top and bottom substrate surfaces; a metallic heat sink filling the aperture; a microwave integrated circuit having a top circuit surface with at least one microwave signal port and a bottom circuit surface in contact with the metallic heat sink; a signal line comprising at least a metallic via between the top and bottom substrate surfaces, and a top signal conductor arranged between the microwave signal port and the metallic via; wherein the dimensions and location of the metallic via are chosen such that the metallic via forms, together with the metallic heat sink, a first impedance-matched non-coaxial transmission line.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 16, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Eric M. Prophet, Florian G. Herrault
  • Patent number: 10943847
    Abstract: A semiconductor device includes a semiconductor chip having an electrode portion and a joining member electrically connected to the electrode portion to allow an electric current to flow in the semiconductor chip through the joining member. The joining member contains a protective material that has a positive temperature coefficient of resistivity, and the positive temperature coefficient of resistivity has a larger value in a temperature range higher than a threshold temperature than in a temperature range lower than the threshold temperature, the threshold temperature being a predetermined temperature lower than a breakdown temperature of the semiconductor chip. The electrode portion of the semiconductor chip may contain the protective material.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiko Sugiura, Tomohito Iwashige, Jun Kawai
  • Patent number: 10937896
    Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Yan Wang
  • Patent number: 10937735
    Abstract: Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jae-Woong Nah, Eric Peter Lewandowski, Adinath Shantinath Narasgond
  • Patent number: 10937711
    Abstract: An electronic device includes: a support member that has a metallic placement surface joined to the conductive bonding layer, and a metallic sealing surface provided on an outer side of the placement surface in an in-plane direction of the placement surface to adjoin the placement surface and to surround the placement surface; and a resin member, which is a synthetic resin molded article, joined to the sealing surface and covering the electronic component. The sealing surface includes a rough surface having a plurality of laser irradiation marks having a substantially circular shape. The rough surface includes a first region and a second region. The second region has a higher density of the laser irradiation marks in the in-plane direction than the first region.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 2, 2021
    Assignee: DENSO CORPORATION
    Inventors: Wataru Kobayashi, Kazuki Koda
  • Patent number: 10937752
    Abstract: Disclosed herein are embodiments of lead-free (Pb-free) or lead-bearing solder column devices that can include an inner core, an outer sleeve surrounding a portion of the inner core, at least one space along a length of the outer sleeve, and a second layer including a solder material coupled with a portion of the inner core within the at least one space. The inner core can be configured to support the solder column so as to prevent a collapse of the solder column at temperatures above a liquidus temperature of the outer sleeve's solder material and the second layer's solder material. The column serves as a heat-sink to conduct excessive heat away from a heat generating semiconductor chip. Moreover, the compliant solder column absorbs strain and mechanical stress caused by a difference in the coefficient of thermal expansion (CTE) connecting the semiconductor chip to a printed circuit board (PCB).
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: March 2, 2021
    Assignee: TopLine Corporation
    Inventor: Martin B. Hart
  • Patent number: 10937654
    Abstract: A method of doping a silicon-containing material. The method comprises forming at least one opening in a silicon-containing material and conformally forming a doped germanium material in the at least one opening and adjacent to the silicon-containing material. A dopant of the doped germanium material is transferred into the silicon-containing material. Methods of forming a semiconductor device are also disclosed, as are semiconductor devices comprising a doped silicon-containing material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Francois H. Fabreguette, John A. Smythe, Witold Kula
  • Patent number: 10937707
    Abstract: A wiring substrate includes an insulating substrate that is square in plan view, the insulating substrate having one main surface with a recess and an other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate and in a peripheral section of the insulating substrate. The external electrodes include first external electrodes and second external electrodes. In plan view, the first external electrodes are located at corners of the insulating substrate, and the second external electrodes are interposed between the first external electrodes. Each of the first external electrodes has a smaller area and a larger width in a direction orthogonal to each side of the insulating substrate than each of the second external electrodes.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 2, 2021
    Assignee: Kyocera Corporation
    Inventor: Hiroshi Kawagoe
  • Patent number: 10914008
    Abstract: An oxygen-free or oxygen-poor solution for the electroless deposition of a platinum group metal is described. The solution includes a ruthenium (II) amine complex having a first oxidation potential, and a platinum group metal compound having a reduction potential larger than the opposite of the oxidation potential of the ruthenium (II) amine complex.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 9, 2021
    Assignee: IMEC VZW
    Inventor: Henricus Philipsen
  • Patent number: 10910338
    Abstract: A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeonghun Go, Jeong-Mo Nam, Sangrock Yoon
  • Patent number: 10910288
    Abstract: An integrated circuit package structure and a package method. The integrated circuit package structure includes: a semiconductor chip, an encapsulation layer covering the semiconductor chip, the encapsulation layer including a first encapsulation layer and a second encapsulation layer alternately stacked, a sum of a number of the first encapsulation layer and a number of the second encapsulation layer being at least 3; wherein a thermal expansion coefficient of one of the first encapsulation layer and the second encapsulation layer is positive, and a thermal expansion coefficient of the other of the first encapsulation layer and the second encapsulation layer is negative.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhidong Wang, Ronghua Lan
  • Patent number: 10903149
    Abstract: A semiconductor module is provided to include: a plurality of semiconductor chips; a lead frame that is connected to the plurality of semiconductor chips; and a main terminal that is connected to the lead frame, wherein the lead frame has an electrical connection portion that electrically connects the plurality of semiconductor chips to the main terminal, and a heat dissipation portion that is provided to extend from the electrical connection portion. The heat dissipation portion does not extend a path of a current that flows between the main terminal and the plurality of semiconductor chips.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: January 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Koichiro Iyama
  • Patent number: 10894712
    Abstract: An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Simon Joshua Jacobs
  • Patent number: 10892251
    Abstract: According to one embodiment, a semiconductor device includes a wiring board, a controller chip that is provided on the wiring board and is sealed with a first resin composition, a nonvolatile memory chip that is provided on the first resin composition and is sealed with a second resin composition, a second bonding wire that connects a pad for electric power supply wiring of the controller chip to the wiring board and is sealed with the first resin composition, and a first bonding wire that connects a pad for signal wiring of the controller chip to the wiring board, is sealed with the first resin composition, and has a higher Pd content than that of the second bonding wire.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: January 12, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Tsukiyama, Hideo Aoki
  • Patent number: 10892441
    Abstract: Provided is a display device, comprising a display panel which comprises a first area and a second area located around the first area; and an under-panel sheet which is located under the display panel and overlaps the first area and the second area, wherein the under-panel sheet comprises a buffer member and a strength reinforcing member, wherein the strength reinforcing member is thinner than the buffer member, and a ratio of a thickness of the buffer member to a thickness of the strength reinforcing member is 3 to 6 times.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 12, 2021
    Inventors: Youn Hwan Jung, Kyu Han Bae, Jae Lok Cha, Kang Yong Lee
  • Patent number: 10886263
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang