Abstract: A method of forming an image detector from an optical detector having a first side connected to a substrate and a second side opposite the first side. The method includes: receiving the detector; electrically coupling the second side of the detector to a read out integrated circuit (ROIC); securing the detector to the ROIC with an adhesive, wherein the adhesive surrounds the detector and at least a portion of the substrate. The method also includes chemically removing at least some of the substrate to expose an exposed portion of the first side of the detector. Such removal results in the formation of an adhesive fence from the adhesive that has a fence upper surface that is above the first side on which an optical element is mounted such that an air gap exists between the first side of the detector and the optical element.

Abstract: A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

Abstract: An image sensor includes a sensor pixel. The sensor pixel includes a first transistor coupled between a first power source and a first node, where the first transistor is turned on in response to a first control signal, a light-sensing element coupled between the first node and a second power source, where the light-sensing element generates photocharges in response to incident light, a storage capacitor coupled in parallel to the light-sensing element between the first node and the second power source, and an amplifier including a plurality of transistors coupled in series between the first power source and an output line, where the amplifier outputs a sensing signal corresponding to a voltage of the first node in response to a first driving signal.

Abstract: A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.

Abstract: The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be ?LEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

Abstract: Provided are a display device and a method of manufacturing a display device. The display device includes a first substrate in which a display area and a non-display area disposed outside the display area are defined; a second substrate which faces the first substrate and comprises an area recessed in a thickness direction and a contact area disposed outside the recessed area; and a cell seal which bonds the first substrate and the second substrate together, wherein the cell seal comprises a bonding filament which is disposed between the contact area and the non-display area to connect the contact area and the first substrate and a frit seal which is disposed between the recessed area and the non-display area.

Abstract: An electronic device includes: a support member that has a metallic placement surface joined to the conductive bonding layer, and a metallic sealing surface provided on an outer side of the placement surface in an in-plane direction of the placement surface to adjoin the placement surface and to surround the placement surface; and a resin member, which is a synthetic resin molded article, joined to the sealing surface and covering the electronic component. The sealing surface includes a rough surface having a plurality of laser irradiation marks having a substantially circular shape. The rough surface includes a first region and a second region. The second region has a higher density of the laser irradiation marks in the in-plane direction than the first region.

Abstract: A multi-chip packaging structure employing millimeter wave includes a substrate material, a first and a second substrate board and an adhesive layer. The substrate material has a first metal pad. The first substrate board has a first and a second integrated circuit, multiple first metal wirings and multiple second metal pads, which are layer-by-layer stacked and electrically connected. The first and second metal pads are electrically connected via at least one metal lead. The adhesive layer is disposed between the substrate material and the first substrate board. The second substrate board has a third and a fourth integrated circuit, multiple second metal wirings and multiple third metal pads, which are layer-by-layer stacked and electrically connected. The electro-conductive boss blocks are respectively electrically connected with the second and third metal pads. Chips and antennas are integrated to integrate signal height and avoid interference and minify the volume.

Abstract: A manufacturing method for manufacturing a stacked substrate by bonding two substrates includes: acquiring information about crystal structures of a plurality of substrates; and determining a combination of two substrates to be bonded to each other, based on the information about the crystal structures. In the manufacturing method described above, the information about the crystal structures may include at least one of plane orientations of bonding surfaces and crystal orientations in a direction in parallel with the bonding surfaces. In the manufacturing methods described above, the determining may include determining a combination of the two substrates with a misalignment amount after bonding being equal to or smaller than a predetermined threshold.

Abstract: Image sensors include a photodiode formed in a substrate material and a transistor coupled to the photodiode. The transistor has a trench structure formed in the substrate material, an isolation layer disposed on the substrate material, and a gate disposed on the isolation layer and extending into the trench structure. The trench structure has a polygonal cross section in a channel width plane, the polygonal cross section defining at least four sidewall portions of the substrate material, which contribute to an effective channel width measured in the channel width plane that is wider than a planar channel width of the transistor.

Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.

Abstract: A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs penetrate through the semiconductor device. The TSVs are adjacent to an edge of the semiconductor device. The first seal ring is disposed on and physically connected to one end of each of the TSVs. The second seal ring is disposed on and physically connected to another end of each of the TSVs.

Abstract: A semiconductor device includes a first wiring board having a first surface mounted with a primary radiator, and a second surface mounted with a semiconductor chip, a second wiring board mounted with a secondary radiator that forms an antenna with the primary radiator, and a third wiring board, arranged between the first and second wiring boards, and forming a predetermined gap with each of the first and second wiring boards. A first board-to-board connection member is arranged between the first and third wiring boards, to form a space between the first and third wiring boards, and regulate the spacing between the first and third wiring boards. A second board-to-board connection member is arranged between the second and third wiring boards, to form a space between the second and third wiring boards, and regulate a spacing between the second and third wiring boards.

Abstract: An array substrate, a manufacturing method thereof, and display panel are provided. Gate scanning lines and Light-shielding conductive layer are electrically connected, so that a width of the gate scanning line is substantially unchanged from the conventional technology to ensure an aperture ratio of a display panel. Therefore, an impedance of the wire used to transmit the scanning electrical signal is reduced, so that the display panel driving power consumption is reduced to increase the corresponding speed of pixel charging and discharging.

Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

Abstract: Image sensors include a substrate material having a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) disposed therein. A plurality of pixel isolators is formed in the substrate material, each pixel isolator being disposed between one of the SPDs and one of the LPDs. A passivation layer is disposed on the substrate material and a buffer layer is disposed on the passivation layer. A plurality of first metal elements is disposed in the buffer layer, each first metal element being disposed over one of the pixel isolators, and a plurality of second metal elements is disposed over the plurality of first metal elements.

Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.

Abstract: The present invention provides a die bonding material containing the following component (A) and a solvent and having a refractive index (nD) at 25° C. of 1.41 to 1.43 and a thixotropic index of 2 or more, a light-emitting device including an adhesive member derived from the die bonding material, and a method for producing the light-emitting device. The die bonding material of the present invention is preferably used for fixing a light emitting element at a predetermined position. Component (A): a curable polysilsesquioxane compound having a repeating unit represented by the following formula (a-1) and satisfying predetermined requirements related to 29Si-NMR and mass average molecular weight (Mw) R1-D-SiO3/2??(a-1) [wherein R1 represents a fluoroalkyl group represented by a compositional formula: CmH(2m?n+1)Fn; m represents an integer of 1 to 10, and n represents an integer of 2 to (2m+1); and D represents a linking group (excluding an alkylene group) for connecting R1 and Si, or a single bond].

Abstract: Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate.