Abstract: An oscillator 10 with a noise reduction function has a memory 80 that memorizes modulation data DM for performing the spread spectrum modulation input from an output terminal fout, a modulation signal output circuit 60 that generates a modulation signal SM from the modulation data DM memorized in the memory 80, and a mixer 53 that overlays the modulation signal SM on the control voltage VC of a voltage control oscillator (VCO) 54 of a PLL circuit 50, and it becomes possible to output a spread spectrum modulated output signal CLv under a specification desired by a user by memorizing in the memory 80 the modulation data DM that corresponds to the spread spectrum modulation the user tries to set.

Abstract: A digital FM demodulator employs a baseband phase lock loop (BBPLL), which is particularly effective for long range reception, for combining and demodulating a pair of signals represented by the mathematical expression A(t)ej&thgr;(t) to result in an approximation of d&thgr;/dt. This approximation is then subjected to an inverse of the linear approximation of the frequency response of the BBPLL that produces a very accurate &thgr;. This is conveniently achieved with a IIR filter whose transfer function happens to be the same as the inverse of the linear approximation of the frequency response of the BBPLL. The derivative is then taken of &thgr; to produce a very accurate d&thgr;/dt, the desired result for the output of an FM demodulator. To aid operation of the BBPLL, the incoming digital intermediate frequency is upsampled by a combination of sample and hold and FIR filtering prior to being processed by the BBPLL.

Abstract: A method and apparatus are provided for reducing a startup interval of a temperature controlled crystal oscillator chip. The method includes the steps of connecting an operating circuit of the temperature controlled crystal oscillator chip into a first configuration to reduce the startup interval following application of power and reconnecting the operating circuit into a second configuration after a predetermined time period.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: A resonant oscillator circuit includes an active device and a resonator that causes the active device to oscillate at a resonant frequency of the resonator. The active device includes one or more transistors that are DC biased using one or more resistors. The bias resistors generate thermal noise that is proportional to the resistance value. An external inductor circuit is connected across the output terminals of the active device and in parallel with the resonator. The external inductor circuit short-out at least some of the thermal noise that is generated by the bias resistors, and thereby reduces the overall phase noise of the resonant oscillator.

Abstract: The invention relates to a method for tuning an adjustable oscillator, in which oscillator at least one resonance circuit is used. The frequency of the oscillator is adjusted by changing the resonance frequency of the at least one resonance circuit by means of a control signal for which a minimum value and a maximum value are selected. In the method at least one target value is selected for the control signal, the frequency of the adjustable oscillator is adjusted to substantially correspond to the target value and the value of the control signal and the target value are compared. When the value of the control signal is substantially different from the target value, a tuning signal is produced to change the resonance frequency of the at least one resonance circuit.

Abstract: A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.

Abstract: The present invention relates to a modulation device MD, which is designed to produce an output signal Vout comprising a succession of pulses. According to the invention, a device of this type includes: two transistors T1 and T2, which are arranged as a differential pair; a capacitive element C, which is connected between the two transistors T1 and T2; adjusting means LC1, LC2, UC1, UC2, in order to adjust the potential of at least one of the terminals of the capacitive element C; and comparing means CMP, which supply the output signal Vout, which is representative of the sign of the voltage Vc, which is present at the terminals of the capacitive element C. By means of a simple and substantially analog structure, the invention permits rapid, flexible control of the width of the pulses of the output signal Vout.

Abstract: A precision, low jitter oscillator circuit is provided that is particularly well-suited for generating a clock signal in miniature digital systems, such as digital hearing aids. The oscillator includes a plurality of differential inverters configured in a feedback loop to generate an oscillating clock signal. The differential inverters include a capacitive trimming network for adjusting the frequency of the oscillating clock signal and employ resistive loads for minimizing jitter in the clock signal. The components of the oscillator are fabricated in a common silicon process to minimize the size of the oscillator.

Abstract: An object of the present invention is to facilitate positioning of a metal member for mounting a high-frequency diode and of a dielectric strip, thereby remarkably improving control of oscillation characteristics and workability in production.

Abstract: A circuit for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes frequency dividers with selectable divisors for the reference and feedback signals, and a phase detector having a charge pump output circuit with selectable output current ranges. During acquisition of phase lock by the PLL, the divisors for the reference and feedback signal frequency dividers are increased by the same factor, and the charge pump current range is increased by the same ratio. As a result, the reference rate is decreased as the charge pump current range is increased simultaneously by the same ratio. Meanwhile, the linear loop bandwidth and phase margin remain substantially constant.

Abstract: A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is reverse to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.

Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.

Abstract: In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.

Abstract: Dedicated registers sequenced by a state machine capture phase locked loop reconfiguration values or parameters and load them into a reconfigurable phase locked loop in order to achieve rapid and reliable reconfiguration with high immunity from clock glitches and jitter as the phase locked loop goes in and out of lock. In the preferred environment of a digital bus, reconfiguration values or parameters can be supplied through a normal bus transaction and no dedicated connections are required for phase locked loop reconfiguration.

Abstract: Feedback methods and systems are provided to achieve rapid switching of oscillator frequencies without compromising operational feedback loop bandwidths that filter out spurious tones and phase noise to thereby enhance loop spectral and noise performance. The methods respond to frequency changes in a reference signal by providing an open-loop drive current to drive a feedback signal towards the reference signal. The drive current is terminated and the feedback control loop closed when the feedback signal is within a predetermined acquisition range of the reference signal. Preferably, the closed loop is initially configured with a first feedback bandwidth and is subsequently reconfigured with a second steady-state feedback bandwidth that is less than the first feedback bandwidth.

Abstract: There is provided a semiconductor integrated circuit device for realizing in the higher accuracy the verification of a plurality of operations of a clock generation circuit to form an internal clock signal and enabling verification for various performances of the internal clock signal generation circuit while simplifying the structure thereof. In such semiconductor integrated circuit device, a measuring circuit for conducting at least two kinds of measurements among the measurements of lock time until the predetermined internal clock signal corresponding to the input clock signal can be obtained, the maximum frequency of the internal clock signal and jitter of the internal clock signal is provided to the clock generation circuit to form the internal clock signal corresponding to the input clock signal inputted from an external terminal. Thereby, operations of the clock generation circuit can be verified with higher accuracy within the semiconductor integrated circuit device.

Abstract: An RF VCO (260A) forms, in the preferred embodiment, a part of a dual mode mobile station (100). Also disclosed is a method for operating the VCO. The VCO is operated in a first frequency band using a first inductance (300A) that forms part of a first resonant circuit (parallel resonance), and the VCO is switched for operation to a second frequency band by the closing a switch (M5) that causes a second resonant circuit (serial resonance) to be inductively coupled to the first resonant circuit. The second resonant circuit includes a second inductance (300B), and preferably includes at least one frequency tunable component, such as a varactor (VR3, VR4), for adjusting the resonant frequency of the second resonant circuit. The second inductance is center tapped, and the switch, such as a MOS transistor, is coupled in series between two ends of the center tapped inductance. The first frequency band may include 3.6 GHz (a double frequency GSM band) and the second frequency band may include 4.

Abstract: A noise elimination circuit which can eliminate all noise of a reset signal of a microprocessor or an input signal effective in a specific logic level comprises: a ring oscillator unit for receiving first and second signals and generating a pulse signal according to the first signal, and stopping generation of the pulse signal when the first and the second signals have a first potential level; and a frequency division unit for receiving an output signal of the ring oscillator unit and then, N times frequency-dividing to generate the signal to the second signal, and being reset by the first signal.

Abstract: A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term “hysteresis” as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.