Patents Examined by David C Spalla
  • Patent number: 10741670
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor structure including a semiconductor substrate, a plurality of semiconductor fin structures, and a plurality of dummy gate structures, each including a dummy insulating layer and a dummy gate electrode; forming a covering layer including a first portion on side surfaces of each dummy gate structure and a second portion on semiconductor fin structures; forming a sacrificial layer on side surfaces of the first portion of the covering layer; forming a first trench and a second trench on two opposite sides of each dummy gate structure; forming a source electrode in each first trench and a drain electrode in each second trench; forming an interlayer dielectric layer; performing a planarization process to expose dummy gate structures; and removing each dummy gate electrode and a portion of the dummy insulating layer to form a trench to expose the semiconductor fin structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 11, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10741727
    Abstract: A light emitting device includes: a substrate; a light emitting element disposed on the substrate; a light transmissive member having a plate shape and having an upper face and a lower face disposed such that the lower face opposes a light emission face of the light emitting element; a light reflecting member covering lateral faces of the light emitting element and lateral faces of the light transmissive member; and a light shielding frame disposed on the upper face of the light reflecting member surrounding the light transmissive member. The light shielding frame has an opening, an inner perimeter of the opening is positioned at a distance apart from an outer perimeter of the upper face of the light transmissive member in a plan view as seen from above, and the light reflecting member is interposed between the inner perimeter of the opening and the outer perimeter of the upper face of the light transmissive member.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 11, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Hiroki Nakai, Kensuke Yamaoka
  • Patent number: 10734543
    Abstract: A method includes mounting a ceramic phosphor (102) on an acrylic-free and metal-containing catalyst-free tacky layer (108) of a dicing tape (104), dicing the ceramic phosphor (102) from the dicing tape (104) into ceramic phosphor plates (11)2, removing the ceramic phosphor plates (112) from the dicing tape (104), and attaching the ceramic phosphor plates (112) on light-emitting device (LED) dies.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 4, 2020
    Assignee: Lumileds LLC
    Inventors: April Schricker, Niek Van Leth, Daniel Roitman
  • Patent number: 10734567
    Abstract: A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte, Mary B. Rothwell
  • Patent number: 10727405
    Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
  • Patent number: 10727391
    Abstract: A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte, Mary B. Rothwell
  • Patent number: 10720508
    Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Scott B. Clendenning, Martin M. Mitan, Szuya S. Liao
  • Patent number: 10720329
    Abstract: A method of manufacturing a semiconductor apparatus includes preparing a semiconductor substrate, and forming a Schottky electrode that is in Schottky contact with a surface of the semiconductor substrate. The Schottky electrode is made of a metal material containing a predetermined concentration of oxygen atoms.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: July 21, 2020
    Assignee: DENSO CORPORATION
    Inventor: Shuhei Ichikawa
  • Patent number: 10720601
    Abstract: A display device is disclosed, which includes: a substrate having a first edge, wherein the first edge is parallel to a first direction, and the substrate has a display region and a border region adjacent to the display region; a first insulating layer disposed on the substrate; a first electrode layer disposed on the first insulating layer; and a second insulting layer disposed on the first electrode layer, wherein the second insulating layer comprises plural protrusions, the protrusions are disposed in the border region, and the protrusions are arranged along the first direction.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 21, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Yun-Sheng Chen, Kuang-Pin Chao, Hsia-Ching Chu, Ming-Chien Sun
  • Patent number: 10720555
    Abstract: A light emitting diode device includes a light emitting diode chip, a wavelength conversion layer including a bottom surface facing a top surface of the light emitting diode chip, and an interlayer having a first portion between the light emitting diode chip and a part of the bottom surface of the wavelength conversion layer, and a second portion extending from the first portion and connected between a remaining part of the bottom surface of the wavelength conversion layer and a side surface of the light emitting diode chip. The second portion has a side surface including a linear surface substantially aligning with a side surface of the wavelength conversion layer, and a curved surface having a first end connected to the linear surface and a second end connected to the side surface of the light emitting diode chip. The linear surface and the curved surface define a chamfer angle.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: July 21, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Hung-Chun Tong, Chang-Zhi Zhong, Fu-Hsin Chen, Yu-Chun Lee
  • Patent number: 10714491
    Abstract: A memory device and manufacturing method thereof are provided. The memory device includes a pair of stacked structures, a charge storage layer, and a channel layer. The stacked structures are disposed on a substrate. Each stacked structure includes gate layers and insulating layers stacked alternately, and a cap layer on the gate layers and the insulating layers. The charge storage layer is disposed on sidewalls of the stacked structures facing each other. The channel layer covers the charge storage layer, and has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the stacked structures. The bottom portion covers a portion of the substrate located between the stacked structures. The body portion is connected between the top and bottom portions. Dopant concentrations of the top and bottom portions are respectively greater than a dopant concentration of the body portion.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: July 14, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Lan Chiu, Chun-Min Cheng
  • Patent number: 10714680
    Abstract: A stack of connecting metal vias is formed on a bottom electrode by repeating steps of depositing a conductive via layer, patterning and trimming the conductive via layer to form a sub 30 nm conductive via, encapsulating the conductive via with a dielectric layer, and exposing a top surface of the conductive via. A MTJ stack is deposited on the encapsulated via stack. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 60 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layers but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layers underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi Yang, Dongna Shen, Yu-Jen Wang
  • Patent number: 10707353
    Abstract: A TFT, a method for fabricating the same, a display substrate, and a display device are disclosed. The TFT comprises a substrate, a gate, a gate insulating layer, semiconductor layer, a source, and a drain. The gate comprises a rough surface on a side facing the semiconductor layer. Since the surface of gate is uneven, the light which has been reflected on the surface of gate will no longer be reflected, or will be directly scattered to other directions. The incident light from the backlight source cannot impinge onto the semiconductor layer by continuous reflection. This reduces the possibility that the semiconductor layer is irradiated by light, and improves stability of TFT.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Qin
  • Patent number: 10700055
    Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 30, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram Ali Salman, Guruvayurappan Mathur, Ryo Tsukahara
  • Patent number: 10700066
    Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10700172
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor body having a first conductivity type, a first major surface and a second major surface opposite the first major surface, a gate arranged on the first major surface, a body region having a second conductivity type opposite the first conductivity type, the body region extending into the semiconductor body from the first major surface, a source region having the first conductivity type, the source region being arranged in the body region, a buried channel shielding region having the second conductivity type, a contact region having the second conductivity type, and a field plate arranged in a trench extending into the semiconductor body from the first major surface.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Franz Hirler, Ralf Siemieniec
  • Patent number: 10693019
    Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
  • Patent number: 10684401
    Abstract: [Object] To make it possible to improve viewing angle characteristics more. [Solution] Provided is a display device including: a plurality of light emitting sections formed on a substrate; and a color filter provided on the light emitting section to correspond to each of the plurality of light emitting sections. The light emitting sections and the color filters are arranged such that, in at least a partial region in a display surface, a relative misalignment between a center of a luminescence surface of the light emitting section and a center of the color filter corresponding to the light emitting section is created in a plane perpendicular to a stacking direction.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: June 16, 2020
    Assignee: Sony Corporation
    Inventor: Daisuke Ueda
  • Patent number: 10686092
    Abstract: The invention aims for an avalanche photodiode comprising an absorption zone (2), a multiplication zone (3), a first electrode and a second electrode. The photodiode further comprises a waveguide (10) forming a curved closed circuit capable of guiding a luminous flux over several turns of said circuit. The absorption zone extends over a portion at least of said waveguide, and the multiplication zone, the first and second electrodes extend along one part at least of the curved closed circuit. The waveguide is preferably an edge waveguide forming a ring and comprising an absorption zone made of germanium of width less than 200 nm. The photodiode according to the invention has an improved compacity and an improved bandwidth while limiting the multiplication noise.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 16, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Karim Hassan, Salim Boutami
  • Patent number: 10672887
    Abstract: A vertical transistor includes a first source/drain region and a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin. A gate dielectric is formed on the fin, and a gate conductor is formed on the gate dielectric in a region of the fin. A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Kangguo Cheng, Theodorus E. Standaert, Veeraraghavan S. Basker