Patents Examined by David C Spalla
  • Patent number: 11374093
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate, a source/drain contact disposed over the substrate, a first dielectric layer disposed on the source drain contact, an etch stop layer disposed on the first dielectric layer, and a source/drain conductive layer disposed in the etch stop layer and the first dielectric layer. The structure further includes a spacer structure disposed in the etch stop layer and the first dielectric layer. The spacer structure surrounds a sidewall of the source/drain conductive layer and includes a first spacer layer having a first portion and a second spacer layer adjacent the first portion of the first spacer layer. The first portion of the first spacer layer and the second spacer layer are separated by an air gap. The structure further includes a seal layer.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11374110
    Abstract: In a gate replacement process, forming a dummy gate and an adjacent structure; In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shiang-Bau Wang
  • Patent number: 11374002
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: June 28, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Wenjun Li, Man Gu
  • Patent number: 11367778
    Abstract: A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Gulbagh Singh, Po-Jen Wang, Kun-Tsang Chuang
  • Patent number: 11367994
    Abstract: A light emitting device includes: a base including: a main body, and a frame disposed on an upper surface of the main body; one or more laser elements disposed on the upper surface of the main body and positioned inward of the frame; and a cover including: a support member that is fixed to an upper surface of the frame and that has an opening inside the frame, and a light transmissive portion that is fixed to the support member and that is disposed so as to close the opening. A first interface, between the light transmissive portion and the support member, is located inward of and lower than a second interface, between the support member and the frame. A portion of the support member that extends at least from an outermost end of the first interface to an innermost end of the second interface has a constant thickness.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: June 21, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Takuya Hashimoto, Eiichiro Okahisa
  • Patent number: 11362109
    Abstract: The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate. A group III nitride transistor is formed in a trench in the SOI substrate. The activation of the group III nitride transistor is controlled by a silicon-based transistor. The silicon-based transistor that includes a portion of a silicon layer of the SOI substrate. A group III nitride transistor device is adjacent to the silicon-based transistor.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ko-Tao Lee, Xin Zhang, Todd Edward Takken
  • Patent number: 11349004
    Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11349000
    Abstract: An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Ryo Kuwana, Isao Hara
  • Patent number: 11342458
    Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Tung-Wen Cheng, Chang-Yin Chen, Mu-Tsang Lin
  • Patent number: 11329055
    Abstract: Semiconductor cell and its forming method and operating method are provided. The semiconductor device includes: a substrate with a first region; a first nanopillar, formed on a substrate surface of the first region and perpendicular to the substrate surface; a first source/drain region, formed at a bottom of the first nanopillar and in a portion of the substrate in the first region; a first gate structure, surrounding the first nanopillar and formed on the first source/drain region; and a second source/drain region, formed at a top of the first nanopillar and on the first gate structure.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11322450
    Abstract: A chip package including a semiconductor die, an insulating encapsulant, and a first redistribution layer is provided. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is provided over the semiconductor die and the encapsulant and includes a first redistribution portion and a second redistribution portion in contact with the first redistribution portion. The first redistribution portion is between the second redistribution portion and the semiconductor die. The first redistribution portion includes a first dielectric portion and a plurality of first conductive features embedded in the first dielectric portion. The plurality of first conductive features electrically connects the semiconductor die to the second redistribution portion. The second redistribution portion includes a second dielectric portion and a plurality of second conductive features embedded in the second dielectric portion and connected to the first conductive features.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chen-Hua Yu, Hung-Jui Kuo
  • Patent number: 11322619
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chao Lin, Wei-Sheng Yun, Tung-Ying Lee
  • Patent number: 11322614
    Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Jin Kim, Dong Woo Kim, Sang Moon Lee, Seung Hun Lee
  • Patent number: 11322409
    Abstract: Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lo-Heng Chang, Chih-Hao Wang, Kuo-Cheng Chiang, Jung-Hung Chang, Pei-Hsun Wang
  • Patent number: 11315925
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11316034
    Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11316046
    Abstract: In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun Hsiung Tsai
  • Patent number: 11316030
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 11315926
    Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deokhan Bae, Sungmin Kim, Juhun Park, Yuri Lee, Yoonyoung Jung, Sooyeon Hong
  • Patent number: 11309265
    Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsun Huang, Po-Han Wang, Ing-Ju Lee, Chao-Lung Chen, Cheng-Ming Wu