Patents Examined by David E. Graybill
  • Patent number: 9403670
    Abstract: A microphone structure of an MEMS device has a layer construction including: a base substrate; a deflectable microphone diaphragm at least partly spanning a through-opening in the substrate; a deflectable electrode of a microphone condenser system; a stationary counter-element having ventilation openings situated in the layer construction over the microphone diaphragm and acting as a bearer for a stationary electrode of the microphone condenser system. The diaphragm is bonded into the layer construction on the substrate via a flexible beam. The otherwise free edge region of the diaphragm is curved in a pan shape, so that it extends both vertically and also in some regions laterally beyond the edge region of the through-opening, and the edge region of the through-opening forms a lower stop for the diaphragm movement.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: August 2, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Christoph Schelling, Stefan Singer, Jochen Zoellin
  • Patent number: 9362196
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: June 7, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
  • Patent number: 9355887
    Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
  • Patent number: 9350360
    Abstract: A system for configuring a semiconductor device to generate an output signal. The system includes a temperature sensor configured to sense a plurality of operating temperatures of the semiconductor device, the plurality of operating temperatures including at least a first operating temperature and a second operating temperature. A controller is configured to determine a plurality of operating frequencies of the output signal at respective operating temperatures of the plurality of operating temperatures. The plurality of operating frequencies include a first operating frequency of the output signal when the semiconductor device is at the first operating temperature and a second operating frequency of the output signal when the semiconductor device is at the second operating temperature. Memory is configured to store calibration information that associates each of the plurality of operating temperatures of the semiconductor device with respective operating frequencies of the plurality of operating frequencies.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 24, 2016
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 9324659
    Abstract: A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungWon Cho, DaeSik Choi, HyungSang Park, DongSoo Moon
  • Patent number: 9305861
    Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Tim Murphy, Lee Gotcher
  • Patent number: 9281206
    Abstract: Methods, systems, and devices are described for slicing and shaping materials using magnetically guided chemical etching. In one aspect, a method includes forming a pattern on a substrate by a mask, depositing a catalytic etcher layer on the patterned substrate, a magnetic guide layer on the etcher layer, and a protection layer on the guide layer, etching the substrate by applying an etching solution to the substrate that chemically reacts with the etcher layer and etches material from the substrate at exposed regions not covered by the mask, steering the composite etching structure into the substrate during the etching by an applied magnetic field that creates a force on the guide layer to direct the etching, in which the steering defines the shape of the sliced regions of the etched substrate, and removing the etched material, the mask, and the composite etching structure to produce a sliced material structure.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: March 8, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Sungho Jin, Young Oh, Chulmin Choi, Dae-Hoon Hong, Tae Kyoung Kim
  • Patent number: 9274413
    Abstract: A method for forming a layout pattern includes the following processes. First, a first layout pattern consisting of mandrel patterns and dummy mandrel patterns, a second layout pattern consisting of geometric patterns, and a third layout pattern consisting of pad patterns and dummy pad patterns, are respectively defined on a first mask, a second mask, and a third mask. Then, the first layout pattern is transferred to form a first patterned layer. Afterwards, spacers having a first critical dimension are formed on the sidewalls of the first patterned layer so as to constitute loop-shaped patterns. Then, the third layout pattern is transferred to form a second patterned layer having a second critical dimension, wherein the second critical dimension is greater than the first critical dimension. Finally, the loop-shaped patterns, the pad patterns, and the dummy pad patterns are transferred into a target layer on the substrate.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 1, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 9269485
    Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided and a plurality of metal layers are formed on the substrate. A spirally patterned conductor layer is formed over and in the substrate and in the metal layers to produce a planar spiral inductor. A via hole is formed over and in the substrate and in the metal layers within the spirally patterned conductor layer, the via hole being formed by a through silicon via (TSV) process. Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface of the metal layers.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chang, Hui-Yu Lee
  • Patent number: 9263292
    Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guy M. Cohen, Steven A. Cordes, Sherif A. Goma, Joanna Rosner, Jeannine M. Trewhella
  • Patent number: 9218956
    Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: December 22, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sampath Purushothaman, Anna W. Topol
  • Patent number: 9214597
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: December 15, 2015
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Patent number: 9214492
    Abstract: The present invention relates to a color and non-visible light e.g. IR sensor, namely a multispectral sensor which can be used in a camera such as a TOF camera for depth measurement, reflectance measurement and color measurement, and for generation of 3D image data or 3D images as well as the camera itself and methods of operating the same.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Softkinetic Sensors N.V.
    Inventors: Ward Van Der Tempel, Daniel Van Nieuwenhove, Maarten Kuijk
  • Patent number: 9190303
    Abstract: A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUDRIES INC.
    Inventors: Douglas C. La Tulipe, Jr., Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9177875
    Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 3, 2015
    Assignee: TAIWAN SEMINCONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Chieh Tsai, Tz-Wei Lin, Sheng-Jen Yang, Hung-Yin Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
  • Patent number: 9177813
    Abstract: In MOSFET having SBD as a protection element, a TiW (alloy having tungsten as a main component) film is used as an aluminum-diffusion barrier metal film below an aluminum source electrode in order to secure properties of SBD. The present inventors have found that a tungsten-based barrier metal film is in the form of columnar grains having a lower barrier property than that of a titanium-based barrier metal film such as TiN so that aluminum spikes are generated relatively easily in a silicon substrate. In the present invention, when a tungsten-based barrier metal film is formed by sputtering as a barrier metal layer between an aluminum-based metal layer and a silicon-based semiconductor layer therebelow, the lower layer is formed by ionization sputtering while applying a bias to the wafer side and the upper layer is formed by sputtering without applying a bias to the wafer side.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: November 3, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuhiko Miura
  • Patent number: 9147597
    Abstract: Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 29, 2015
    Assignee: Peking University
    Inventors: Ming Li, Min Li, Ru Huang, Xia An, Xing Zhang
  • Patent number: 9142807
    Abstract: The present invention provides a method for manufacturing an OLED panel. The method is simple and fixes a first substrate and a flexible material layer together by forming a support layer on the first substrate and forming, through etching, a groove in the support layer and coating UV resin in the groove so as to obtain a flexible material layer that is flat, operable, and not prone to deformation. After the formation of an OLED element, the portion outside an area delimited by the groove is trimmed off and the first substrate and the flexible material layer are separated to obtain a flexible OLED panel. This method allows for automation and does not cause damage to the components.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 22, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Weijing Zeng, Chihche Liu
  • Patent number: 9095773
    Abstract: The present disclosure provides a gaming system including a game controller arranged to generate a skill outcome in response to an input from a player and that is at least partially dependent on a skill of the player. The game controller is arranged to generate an artificial outcome that is controlled by the game controller. The gaming system also includes a game outcome controller arranged to generate a game outcome based on a criterion such that, if the criterion is met, the game outcome is at least partially determined by one of the skill outcome and the artificial outcome and, if the criterion is not met, the game outcome is at least partially determined by the other one of the skill outcome and the artificial outcome. A reward allocator is arranged to allocate a reward that is at least partially dependent on the game outcome.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: August 4, 2015
    Assignee: Aristocrat Technologies Australia PTY Limited
    Inventor: Boris Mitelman
  • Patent number: 9095054
    Abstract: A four quadrant power module with lower substrate parallel power paths and upper substrate equidistant clock tree timing utilizing parallel leg construction in a captive fastener power module housing.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: July 28, 2015
    Assignee: Arkansas Power Electronics International, Inc.
    Inventors: Jack Bourne, Jared Hornberger, Alex Lostetter, Brice McPherson, Ty McNutt, Brad Reese, Marcelo Schupbach, Robert Shaw, Eric Cole, Leonard Schaper